M17x - FSB:DRAM Ratio & CAS Latency

First a quick definition

The point of this thread is to see how we can manipulate the memory settings to achieve a higher OC.

The first way is to find what the best memory dividers are for the M17x. What I found to be the most stable was a 1:2 divider. That means I set my memory speed and fsb speed to the same frequency. This is a 1:2 divider and not a 1:1 because you need to think in terms of actual speed.

To figure out the frequency of DDR (Double Data Rate) memory you need to divide the number in your bios by 2. So 1333Mhz memory has a frequency of 666Mhz. To get the bus speed of your system you need to divide the FSB by 4. So a FSB of 1333 has a bus speed of 333. So the divider is 333:666 or 1:2.

Here are some screen shots of CPU-Z but it's NOT from my M17x that may make it easier to understand. In this example the 199:266 frequency equals a 3:4 ratio.



Here's the JEDEC DDR3 standards

The sceond way is through memory timings. The Nvidia system tools will let you change your memory timings but not the CL (Cas Latency). We need more research in this area to find out the best way to improve this. I own a pair of 2GB Kingston HyperX 1066 memory sticks rated up to 5-5-5-15 and I'm willing to sacrfice them if need be to try to actually achieve those timings. By default the 1066 memory running at 1066 has a CL of 7 and 1333 memory running at 1333 has a CL of 9.

Any input in trying to achieve these two goals would be appreciated.

A couple of important links: Link1, Link2

Some OC CPU-Z screen shots

Stock


Multi=9.5, FSB=1333, Mem=1333


Multi=12, FSB=1066, Mem=1333


Multi=10, FSB=1280, Mem=1280


This is the highest CPU Freq I got but it didn't last long before BSOD.

 

i know how that damn divisor sub menu i have been trying to figure out for 7 hours now

 

A couple of important links: Link1, Link2

I just added this to the OP in case it gets missed.

 

I'm not 100% sure what that will even do for us at this point. Plus that won't help us with the timings.

 

true .... my most stable timing was

4:5 i think


either which way i ran out of voltage since non extreme PU's can't get your 1.357 v's

yes i looked up the Vcores in BIOS

 

The divisor options would make easier to select divisors since you don't have to do the maths but that's it.

Anyway I'm gonna do a paint of some useful maths and post here soon.

 

I take it this didn't work again?

 

no maybe im retarded but i push the first on let go then pushed the 2 one ...

in my massive spamming i found a glitch

press ctrl alt S

 

I'm not in front of my M17x. What does it do?

 

it used to be a old command but they edited it out now it does BLAH

 

So if there was a way to get in to some kind of "engineering mode" do you think you would have found it by now with all your attempts?

 

well i the BIOS strings is where i found manufacturer mode ..... it could be hidden somewhere or just in the BIOS code its self to be blank

 

I don't want to start a new thread for this question so here it is:

Why is it better when OC to have a faster memory speed than FSB? Can someone tell me the exact correlation in between the two?

Here is what I understand:

FSB speed is the speed at which the CPU communicates with the RAM. If the RAM's speed is less than the FSB than information is just waiting to be processed creating a bottleneck. Correct?

 

FSB is the bandwidth between the CPU and Northbridge.

It's actually best to have the FSB and Memory speed be the same, a 1:1 ratio. There are other dividers that work well but 1:1 is optimal.

IF the FSB speed (not memory) is too slow the proc will be sitting there waiting for info creating a bottleneck.....make sense?

 

Yes, I understand better. Thank you

 

Ok but then what you are saying is that it would be better to have the RAM just a bit faster than FSB to be sure that there is no bottleneck right?

 

No you'd still would want everything the same speed if possible.

In our case the closest I got was 5:6 but it wasn't stable. BIGX has mentioned some good divisors as 4:5 or 5:6 which means yes the memory is a little faster. It's basically impossible for us with the M17x to get the FSB faster since the slowest the memory can run is at 400Mhz and the fastest I got the bus up to was 370mhz. So we run the memory faster because we don't have a choice right now.

 

I always thought 1:1 was best for ddr2 and 2:1 is best for ddr3? I may be wrong but coming from the desktop world this was my understanding.

so FSB=1333 (4*333)
DDR2=667
DDR3=1333

 

Can I get you to explain this a little further? I'm not following.

 

pretty much, ddr2 works as base fsb*2 where ddr3 works as base fsb*4 so no divisors needed, the base for mem and cpu is 1:1 (333 in my example)

 

From what I understand the only difference between DDR2 and DDR3 is latency and speed. They're both still Double Data Rate running 2 times the memory bus....I could be wrong. I've been wrong lots of times.

 

the speeds are directly related to what I just said.....so is it feasible?

 

could also the fact of triple channel be a factor vice dual?
seems to me this makes sense in both what scook9 says and an extra bank.

 

No triple channel has nothing do with this, as core 2 uses dual channel and core i7 uses triple, but they use the same ram at the same speeds.

The effect of triple vs dual is similar to have RAID in hdd's, you can read/write to 2 simultaneously instead of just one allowing for greater throughput

 

What I meant by speed is really top speed. You can check out the speed of your dram by looking at cpu-z.

 

ok brain freeze....i just realized that notebooks only have daul channel still anyway....my bad.

so bascially your saying different arcitecture (spelling and to lazy to chk it) may be the result of allowing the 2:1 vice 1:1...

 

So i did some reading in the all knowing wikipedia and I think what i got it is correct. The ram also buffers its data different between the actual ram cells and the data bus (fsb?) which is supposed to make it faster. DDR3 uses a wider buffer than ddr2 and some other things like that.

For anyone interested:
http://en.wikipedia.org/wiki/Ddr3

 

I am saying that different architecture determines whether your are using dual channel or triple channel. But the actual speed that the ram operates at (divisors and bus frequencies) is determined by the memory controller which (until x58 and i7) is located in the northbridge for Intel CPUs

 

gotcha now....
so i was a bit correct when stating architecture, but since you mention controller and northbridge, it fits better.
i have read before about that, and just plum spaced it all...
(ugh...getting old sucks)

 

I will try to sum up what I know/understand into one post:

You first start with your system clock (also called FSB) - for all examples I will use 266 MHz as this is what we are dealing with in our current notebooks.

This is sometimes also represented as 4 times this number due to the FSB of these chipsets being what is known as a quad-pumped FSB (266*4=1066 MHz) So fsb can be said as either 266 MHz or 1066 MHz (I will use the 266 though)

This base clock will be used to determine both your RAM and CPU operating speeds.

For CPU: FSB*Multiplier=Operating speed (266*9.5=2527 MHz) (Qx9300,T9400,P9500)

For Ram: it is a little more complicated and this is where the divisors come into play

For divisor (FSB:Ram Base Clock)

1:1
266*4=1066 MHz (DDR3)

4:3
266*3/4=200 MHz
200*4=800 MHz (DDR3)

and so on

I am a little hazy on how DDR2 gets defined with the divisors I will admit. I know that on a 1333 FSB both DDR2 667 and DDR2 800 are common and DDR2 1066 is supported sometimes (these are all due to divisors but the DDR2 667 is 1:1. I know that for sure - so that's 333*2=667)

Ratios that are common with ram,

266 => 200 is 4:3 as shown above
266 => 266 is 1:1 (duh)
266 => 333 is 4:5 (I think this is how 333 runs on the m17x)
333 => 400 is 5:6 (pretty sure this is the common for desktops running DDR2-800)

Hope this helps some

 

helps yes....i have never been a fan of how they promote memory speeds.
while engineers and most in the tech world can relate and understand, the average person gets suckered into larger numbers, and most for no seeable reason other then the number...(1600 vs. 1333)

so how does CAS latency play when using divisors? better numbers at lower divisors? why cant you have the rated CAS at any speed?

 

The CAS (and all other) latency is used to align the ram bus and data bus (data being between CPU/RAM and RAM being between the databus and actual memory chips). Since the operations do not always happen on the same clock cycle, this latency (which is a measure of how many clock cycles to stall operation) allows the 2 busses to sync up and ensure the proper transmission of data.

I am an EE student and just finished a class on computer design (pretty much cpu design and how the cpu ram and cache interact) so this is still kind of fresh for me haha - although I didn't learn anything at the level of Intel....just rudimentary processor design - definitely still helps though

 

the wikipedia article I linked also explained it well (although may have made more sense to me than you due to my higher exposure to the topic via aforementioned classes)

 

word....thx for all the info.

 

glad to help.

 

ehem....i did...but just fyi for future...
we mods delete lines asking for rep...as i had to in your other thread...

reps will come - just cant ask....

 

oh, ok, didn't know, sorry bout that

removed it myself so you don't have to

 

1:1 would be DDR3-667 (what doesn't exist by JEDEC standards) since DDR3 still dual pumped .

You forget that DDR is dual pumped .

 

What you are saying is taken into consideration by me saying that ddr2 uses *2 and ddr3 uses *4 I believe.

The divisor is just used to alter the base speed for the ram.

 

DDR-3 is dual pumped not quad pumped. It's double data rate not quad data rate .

 

I have been toying around with some different things since i tossed in the Qx9300 yesterday like 1266 FSB 1333 ram @9.5x or 1333/1333 @9x . havent found the exact sweet spot yet since im still tinkering away.

 

all that (edit: that= Double Data Rate) means is that data is sent on the rising and falling edge of the clock signal dude....

edit: to clarify, the clock signal is a square wave - well not exactly as that is impossible with modern electronics, but VERY close to a square wave

 

I really don't understood your point in saying that, what this change in what are we talking?. BTW i know .

DDR-3 data rate is twice of DDR-2 but this doesn't make it quad pumped .

 

you were the one who said it was quad pumped not me....my points is that DDR has nothing to do with the multiplier against the base clock, that is what is denoted by the 2 or 3 (they also represent different memory architectures - different buffers and such)

The "data rate" is established still by the base ram clock (the part that is effected by the divisor) and is thus the PC-8500 PC-10666 PC-12800 number you see with ram, this is the same for DDR2 and DDR3 as they utilize the same base clock. DDR3 just has the actual memory chips clocked twice as high as comparable DDR2 (comparable being the same base ram clock due to divisor)(I may have this part wrong, as PC2-6400 is DDR2-800 and PC3-6400 is DDR3-800 but I think I am on the right track). This higher clock is also why a higher latency is needed, the end result is that more clock cycles when they are shorter cycles comes out to slightly quicker than the DDr2 even though it has a seemingly much lower latency.

I think we are somewhat on the same page but losing something in the communication haha

 

I don't said it . Yes you r right.

TBH i think i don't know what and why we are talking anymore lol

 

Cool, I wasn't arguing, just like to understand how this stuff works haha

 

That what I was trying to say earlier. If I knew this discussion was going to happen I wouldn't have taken a long lunch.

 

You keep multiplying by 4 that's why he said quad pumped.

 

I think we are still having a misunderstanding/disagreement about what 1:1 means.....

I am saying that the 1:1 (or any ratio) is referring to the BASE CLOCK FOR THE RAM not the end speed.....and this ratio/base clock is determined the exact same way for DDR2 OR DDR3. The end speed is determined by multiplying that base clock by 2 for DDR2 or by 4 for DDR3

DDR != dual pumped
people seem to have a lot of trouble with this

edit: I was wrong here and DDR can be referred to as dual pumped - thanks for clarifying this for me BIGX333

 

What you just said is exactly right but it did not come across that way in your earlier posts. Go back and read them.