M17x - FSB:DRAM Ratio & CAS Latency

"The primary benefit of DDR3 is the ability to transfer at twice the data rate of DDR2 (I/O at 8× the data rate of the memory cells it contains), thus enabling higher bus rates and higher peak rates than earlier memory technologies"

Copy and pasted from the wikipedia page about DDR3

More copy and paste:

From DDR2 Page:
With data being transferred 64 bits at a time, DDR2 SDRAM gives a transfer rate of (memory clock rate) × 2 (for bus clock multiplier) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR2 SDRAM gives a maximum transfer rate of 3200 MB/s.

From DDR3 Page:
With data being transferred 64 bits at a time per memory module, DDR3 SDRAM gives a transfer rate of (memory clock rate) × 4 (for bus clock multiplier) × 2 (for data rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR3 SDRAM gives a maximum transfer rate of 6400 MB/s.

 

This is what I'm talking about.

 

the bus multipliers are correct actually, I believe the problem is arising from a wrong use of the word "quad-pumped" I did not refer to ANYHTING as ANY type of pumped except the FSB (as in 333 => 1333) just to clarify

 

In the end we are talking about the same thing. I'm just trying to say it came across confusing early on...maybe it was just me but BIGX seem to have the same confusion.

 

I just want to understand how my system works haha

Any help from you guys is greatly appreciated!

I am not even going to try to pretend to know everything about these computers lol

 

Once you get the M17x you can help us find the right divider for the system. I played with my dividers for a couple hours yesterday and going away from 1:2 makes my system less stable.

 

I am looking forward to it!

I just can't own a system without knowing what the MAX OC is (even though it will still spend %95 of the time at stock haha)

 

1 - DDR IS dual pumped and MEANS dual pumped.

http://en.wikipedia.org/wiki/Pumping_(computer_systems)

More info about DOUBLE data rate:

http://www.corsair.com/memory_basics/index.html


If your DDR- 1 memory clock is 100, the bus speed is 100
If your DDR- 2 memory clock is 100, the bus speed is 200
If your DDR- 3 memory clock is 100, the bus speed is 400

So if you use a QX9300 (266 quad pumped) and DDR-2 533 memory (133 memory clock with x2 multiplier) you have 1:1 as your bus clock is 266 in proc and memory.

If you use a QX9300 (266 quad pumped) and DDR-3 1066 memory (133 memory clock with x4 multiplier) you have 1:2 since your memory bus clock is 533 and your processor bus clock is 266.

But yes dual pump + bus multiplier is totally misleading

 

266 quad pumped is 1066 though....and the 1066 number is actually pointless for the discussion we are having, only that base of 266 is relevant (not to be confused with DDR3-1066)

And the base should be 266 not 133 in your qx9300 examples

Nice presentation from corsair though, I will look at it more in depth when I get home from work.

edit: After reading your post a few more times, I actually cant figure out where you got the 133 numbers at all. And the mentioning of quad pumped is still irrelevant to what we are discussing (at least where you mentioned it in your examples)

 

You don't got it .

133 is the internal memory clock which is multiplied by 2 (in DDR-2) and by 4 (in DDR-3) and the result is the bus speed (266 in DDR-2).

The relevance is between FSB and the BUS speed. The unique thing that DDR-3 changed is how much internal clock you need to get the same bus speed.

DDR-2 1066 works at 266 internal clock and give you 533 bus speed.
DDR-3 1066 works at 133 internal clock and give you 533 bus speed.

This doesn't change the fact that 533 bus speed dual pump (1066) isn't 1:1 with 266 FSB which is quad pump (1066).

 

All I am sure about is that my examples and explanations still make perfect sense (at least to me) and explain exactly how you go from the base system clock to the final cpu and ram speeds...

I am not trying to prove you right or wrong here

 

They don't make sense since you r doing the math with quad pump and DDR is dual pump .

DDR-3 1066 still 533 * 2, the UNIQUE thing that changed (at least in this context since I'm not talking about power consumption, latencies, etc) is how the internal clock became the bus speed which is irrelevant in your examples.

Me too. I'm just trying to explain

 

My understanding is that at the bottom most level, before any "pumping" takes place, there is a base clock or system clock (whatever you want to call it). I know this as the FSB (from my desktop experience).

I am only under the assumption that both the memory and cpu run relative to this base clock I am calling the FSB. In the example of the M17x (at stock speed) FSB= 266 MHz

We do not need to discuss the CPU speed as that is pretty straight forward.

What I thought is happening is that this FSB simply gets multiplied by 2 for DDR2 and 4 for DDR3 to give you the resulting memory frequencies.

Evidence to a theory like mine is the way the Core i7 and X58 chipset work with memory (X58 actually doesn't do anything though as the CPU interacts directly with the memory). In an i7 system, there is a single clock, called bclk (base clock). At stock speeds this is 133 MHz (completely independent example from the M17x so please do not get confused) and the CPU speed as well as RAM speed are just direct multipliers off of this bclk speed. Although I understand that this system does away with a need for divisors and an fsb and may simplify this somewhat.

If I understand what you are saying, then the FSB (I say FSB really just meaning the lowest level common clock used by the 2 systems - CPU and RAM) only shows as 266 but is really 133?

I think we may be getting somewhere now haha

 

You said that u had electronic/low level computing lessons so I'm gonna presume that you know how bus work.

the FSB base clock is 266mhz but the memory chip clock is 266mhz for DDR-2 1066 and 133mhz for DDR-3 1066.

You used wikipedia as source and while i don't like wikipedia I'm gonna quote the same page you used:

With data being transferred 64 bits at a time per memory module, DDR3 SDRAM gives a transfer rate of (memory clock rate) × 4 (for bus clock multiplier) × 2 (for data rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR3 SDRAM gives a maximum transfer rate of 6400 MB/s.

It don't multiply the bus but the chip clock so while DDR-2 needs 266mhz to have 533mhz bus (DDR-2 1066 modules) DDR-3 only needs 133mhz .

DDR-3 still dual pumped, what was changed is the multiplying factor which is used in the internal clock to get the bus clock.

DDR-2 533 is 1:1 with 1066 FSB just as DDR-3 533 (which doesn't exists) would be and DDR-2 1066 is 1:2 with FSB 1066 just as DDR-3 1066 is .

So... DDR-2 1066 is:

266 internal clock, 533 bus, 1066 dual pumped.

and DDR-3 1066:

133 internal clock, 533 bus, 1066 dual pumped.

Just as DDR-2 533 (1:1 with 266 FSB) is:

133 internal clock, 266 bus, 533 dual pumped.

The advantage in DDR-3 is that with a chip running at the same clock speed of DDR-2 you get twice the bandwidth .

 

Since you guys LOVE wiki so much here's some nice charts explaining things. Please take note of Memory clock, Bus clock and Data rate. I think you guys are saying the same thing and it's just a matter of nomenclature. I think I'll put this in the OP.

 

Just as i promised some useful maths:

Calculating CPU clock based on FSB:

Divide your FSB (1333 in this example) by 4 (quad pump):



Now you multiple by the mult (9x [p8600] in this example) and have the clock (2997mhz in this case):





Calculating which settings you need to use a determined divisor:

I'm gonna use 4:5 in this example.





Determining which divisor are you using:

1333 FSB, 1066 MEM.







Z:X .

I need to sleep

 

Thanks BIGX, I'll add it to the OP. I asked for this explanation a while ago....thought you just ignored me.

 

did i mention how much i hate alergbra and how i never wanted to touch it again ?

 

haha Algebra is just the beginning......

 

near the beginning...i thought I understood...at least partially..what you guys were saying...now I am so lost I don't even remember why I read this ; )

i am planning on getting a M17x, i guess for OC'ing I'll just have to ask you guys for help regarding what to do exactly lol, cause I suck at math

for the RAM, I would want to get the 1333 if I have hte money to spare right?

 

no its essentially a waste

 

so it doesn't have any benefits whatsover?

 

lower CL @ 1333 ?

 

Yea thats the only difference really . i have ran both in my machine and neither brought better performance over the other. Also overclocking the CPU i did not get any more stability or higher overclocks after trying both.

 

I decided to flash my own bios last night. Found some anomalies in the strings but it didn't make a difference. The search continues.

 

So you edited the bios and then flashed it but those settings did not appear after the fact ?.

 

Correct. The bios looks the same as the original.

 

Were there any settings in the bios to adjust things like Voltage ?.

 

Yeah you can pretty much see everything. Understanding what and how to change is another story.

 

Yeah im sure its a bit messy unless you really know what your doing in there.

Did you see anything relating to the screen dim or auto contrasting in there?.

 

nope

/10 char

 

imma look @ the new one


it messey but looks like baby changes ill flash tommorw and if i can OC higher ince im tried and don't wanna screw up

 

I really don't want this thread to be forgotten. bump.

 

Not forgotten (for me at least)

In my bookmarks

 

Scytus is paranoiac with memory

 

That's a good thing. Unfortunately this discussion isn't popular. WHEN I find the answers I'll keep it to myself.

 

No! I knew you were going to do this to me, I KNEW IT

Nowhere is safe, NOONE IS SAFE.

 

I'll PM the people who care and hold them to secrecy.

 

And what are the questions ?

 

What is the answer to life, the universe and everything.....

Actually it's the questions proposed in the original post.

 

42

BTW... let me read it again lol

 

The answer is 42

 

See there's still some true geeks here at NBR.

 

for non nerds


http://en.wikipedia.org/wiki/42_(number)

 

conspirators...with your...secret codes

I pull out rule 15..
I wash my hands of this madness

 

@scythus, rule 16 > rule 15

@mandrake

If you want to find the best divisor theres only one way... test it

Which is your max clock and which are the settings?, when your system start to became unstable?, let's start from this .

About the SPD... Have you tried spdtool 0.63? ( http://www.techpowerup.com/spdtool/SPDTool_063.zip)

 

I did test it. The closest I got to 1:1 was 370:400. 375 BSOD's. So I need a new divisor to attempt .

I tested out spdtool a few weeks ago. My memory is bad enough that I don't remember what the issue was with it. I can try it again.

 

If you let M17x choose the divisor it will eventually use a bad divisor so you will need a bit of planning.

You have settings with higher overclock which let you boot windows but it doesn't pass on OCCT or bsod when booting windows?, we need some control to check if the stability is better or not.

If yes, tell me which is.

 

I have a lot of options because I can change my multiplier. Keeping it default at 11.5 I can push the fsb to 1220 stable. If I want to run it higher I can simply lower my multiplier. My options are wide open, the ceiling on the fsb is 1480.

 

I'm not Santa Claus but here is yours Christmas present mandrake:

Code:

/**
 * Calculate possible divisors
 * @author Nelson Luiz "BIGX333" Ferraz de Camargo Penteado
 */
class Divisors {
	
	var $clock;
	var $divisors = array(0.8, 0.66666666666666666666666666666667, 0.625, 0.6, 0.5, 1.25, 1.5, 1.6, 1.6666666666666666666666666666667, 2);
	
	function __construct() {
		if (!empty($_POST['clock'])) {
			$this->clock = $_POST['clock'];
			for($m=8.5;$m<=16.0;$m += 0.5){
				for($f=800;$f<=1333;$f++){
					if (((($f / 4) * $m) <= ($this->clock + 5)) && ((($f / 4) * $m) >= ($this->clock - 5))) {
						foreach ($this->divisors as $value) {
							if ($f * ($value) >= 800 && $f * ($value) <= 1333) {
								if (strpos(($f * ($value)), '.')) {
									if (strlen(substr(strstr(($f * $value), "."), 1)) <= 1) {
										if (substr(strstr(($f * $value), "."), 1) <= 5) {
											$this->doPrint($m, $f, $value);
										}
									}
								} else {
									$this->doPrint($m, $f, $value);
								}
							}
						}
					}
				}
			}		
		}
	}
	
	function doPrint($m, $f, $value) {
		echo "Clock: ".(($f / 4) * $m)." | Mult: {$m}x | FSB: ".($f)." | Memory: ".($f * $value)." | Divisor: ";
		if ($value == 0.8) {
			echo "4:5";
		} elseif ($value == 0.66666666666666666666666666666667) {
			echo "2:3";
		} elseif ($value == 0.625) {
			echo "5:8";
		} elseif ($value == 0.6) {
			echo "3:5";
		} elseif ($value == 0.5) {
			echo "1:2";
		} elseif ($value == 1) {
			echo "1:1";
		} elseif ($value == 1.25) {
			echo "5:4";
		} elseif ($value == 1.5) {
			echo "3:2";
		} elseif ($value == 1.6) {
			echo "8:5";
		} elseif ($value == 1.6666666666666666666666666666667) {
			echo "5:3";
		} elseif ($value == 2) {
			echo "2:1";
		}
		echo "[br][/br]";
	}
}
$Divisors = new Divisors;

http://tehpwnerer.net/divisor.php

Clock: 3547.5 | Mult: 11x | FSB: 1290 | Memory: 1032 | Divisor: 4:5
Clock: 3547.5 | Mult: 11x | FSB: 1290 | Memory: 860 | Divisor: 2:3
Clock: 3553 | Mult: 11x | FSB: 1292 | Memory: 807.5 | Divisor: 5:8
Clock: 3547.75 | Mult: 11.5x | FSB: 1234 | Memory: 987.2 | Divisor: 4:5
Clock: 3550.625 | Mult: 11.5x | FSB: 1235 | Memory: 988 | Divisor: 4:5
Clock: 3553.5 | Mult: 11.5x | FSB: 1236 | Memory: 824 | Divisor: 2:3
Clock: 3549 | Mult: 12x | FSB: 1183 | Memory: 946.4 | Divisor: 4:5
Clock: 3552 | Mult: 12x | FSB: 1184 | Memory: 947.2 | Divisor: 4:5
Clock: 3555 | Mult: 12x | FSB: 1185 | Memory: 948 | Divisor: 4:5
Clock: 3546.875 | Mult: 12.5x | FSB: 1135 | Memory: 908 | Divisor: 4:5
Clock: 3552.25 | Mult: 13x | FSB: 1093 | Memory: 874.4 | Divisor: 4:5
Clock: 3550.5 | Mult: 13.5x | FSB: 1052 | Memory: 1315 | Divisor: 5:4
Clock: 3553.875 | Mult: 13.5x | FSB: 1053 | Memory: 842.4 | Divisor: 4:5
Clock: 3545.5 | Mult: 14x | FSB: 1013 | Memory: 810.4 | Divisor: 4:5
Clock: 3549 | Mult: 14x | FSB: 1014 | Memory: 811.2 | Divisor: 4:5
Clock: 3549 | Mult: 14x | FSB: 1014 | Memory: 1267.5 | Divisor: 5:4
Clock: 3552.5 | Mult: 14x | FSB: 1015 | Memory: 812 | Divisor: 4:5
Clock: 3545.25 | Mult: 14.5x | FSB: 978 | Memory: 1222.5 | Divisor: 5:4
Clock: 3552.5 | Mult: 14.5x | FSB: 980 | Memory: 1225 | Divisor: 5:4
Clock: 3547.5 | Mult: 15x | FSB: 946 | Memory: 1182.5 | Divisor: 5:4
Clock: 3555 | Mult: 15x | FSB: 948 | Memory: 1185 | Divisor: 5:4
Clock: 3549.5 | Mult: 15.5x | FSB: 916 | Memory: 1145 | Divisor: 5:4
Clock: 3548 | Mult: 16x | FSB: 887 | Memory: 1330.5 | Divisor: 3:2
Clock: 3552 | Mult: 16x | FSB: 888 | Memory: 1110 | Divisor: 5:4
Clock: 3552 | Mult: 16x | FSB: 888 | Memory: 1332 | Divisor: 3:2