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    soldering PCI-E X16 instead of integrated graphics card (help)

    Discussion in 'e-GPU (External Graphics) Discussion' started by Rochimaro, Dec 25, 2014.

  1. Rochimaro

    Rochimaro Newbie

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    Hello sorry for the English, I'm from Ukraine:hi2: sings use Google translator

    So when people saw an article instead of soldered GPU PCI-E X1 slot and decided to do the same thing but x16 pinout but I cant find anywhere else than you can help please

    Article Sprites mods - Adding SATA and PCIE to a HP T5325 thin client - The PCI-Express port

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    LA561 (1).jpg
    LA562.jpg

    shematik Documents of my laptop Схемы к ноутбукам IBM Lenovo Ideapad G460 (la-5751p) 54.PNG

    Intel® Core™ i7-600/i5-500/i5-400/i3-300 Processor Series
    PCI Express* Configuration Address Space
    PCIEXBAR has moved to the CPU. The CPU now detects memory accesses targeting
    PCIEXBAR. BIOS must assign this address range such that it will not conflict with any
    other address ranges.
    1.2.5 PCI Express Graphics Attach (PEG)
    The GMCH can be programmed to direct memory accesses to a PCI Express interface.
    When addresses are within either of two ranges specified via registers in each PEG(s)
    configuration space.
    • The first range is controlled via the Memory Base Register (MBASE) and Memory
    Limit Register (MLIMIT) registers.
    • The second range is controlled via the Pre-fetchable Memory Base (PMBASE) and
    Pre-fetchable Memory Limit (PMLIMIT) registers.
    Conceptually, address decoding for each range follows the same basic concept. The top
    12 bits of the respective Memory Base and Memory Limit registers correspond to
    address bits A[31:20] of a memory address. For the purpose of address decoding, the
    GMCH assumes that address bits A[19:0] of the memory base are zero and that
    address bits A[19:0] of the memory limit address are F_FFFFh. This forces each
    memory address range to be aligned to 1-MB boundary and to have a size granularity
    of 1 MB.
    The GMCH positively decodes memory accesses to PCI Express memory address space
    as defined by the following equations:
    Memory_Base_Address  Address  Memory_Limit_Address
    Prefetchable_Memory_Base_Address  Address  Prefetchable_Memory_Limit_Address
    The window size is programmed by the plug-and-play configuration software. The
    window size depends on the size of memory claimed by the PCI Express device.
    Normally these ranges will reside above the Top-of-Low Usable-DRAM and below High
    BIOS and APIC address ranges. They must reside above the top of low memory
    (TOLUD) if they reside below 4 GB and must reside above top of upper memory
    (TOUUD) if they reside above 4 GB or they will steal physical DRAM memory space.
    It is essential to support a separate Pre-fetchable range in order to apply USWC
    attribute (from the processor point of view) to that range. The USWC attribute is used
    by the processor for write combining.Datasheet 35
    Processor Configuration Registers
    Note that the GMCH memory range registers described above are used to allocate
    memory address space for any PCI Express devices sitting on PCI Express that require
    such a window.
    The PCICMD1 register can override the routing of memory accesses to PCI Express. In
    other words, the memory access enable bit must be set to enable the memory base/
    limit and pre-fetchable base/limit windows.
    For the processor, the upper PMUBASE/PMULIMIT registers have been implemented for
    PCI Express Spec compliance. The processor locates MMIO space above 4 GB using
    these registers.

    http://s015.radikal.ru/i331/1412/86/f0585f5e65f6.jpg
    [​IMG]
     

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    Last edited: Dec 26, 2014
  2. Rochimaro

    Rochimaro Newbie

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  3. Rochimaro

    Rochimaro Newbie

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  4. t456

    t456 1977-09-05, 12:56:00 UTC

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    Did a quick search, but couldn't find other schematics than those you already have. But isn't the gpu pinout superfluous? You already have the cpu pinout and the main threads to the gpu are exposed; <strike>scrape off the top and</strike> use multimeter to check which cpu pin connects to which thread on the mb pcb.

    Edit: don't even need to expose the threads; just connect with the capacitors to close the circuit. Then, instead of desoldering the gpu, make a clear cut through the whole set and solder your new wires to the tail-end of the capacitors. Assume you plan to hook them up to something like this x16 tester board?
     
  5. Rochimaro

    Rochimaro Newbie

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    I'm not sure that a valid PINOUT on pci ex x16 slot [​IMG]