AMD Turion vs. Intel Core 2 Duo

What's the consensus about which one is better (comparable speeds)?

 

Intel Core 2 duo.

 

core 2 duo no contest.

 

Intel Core 2 Duo is a more powerful cpu clock for clock.

There are tales of the AMD Turion X2s being able to handle ram quicker, but this is not proven.

 

the new 65nm Turion X2's are comparable with speeds reaching 2.4 GHz. as I last remember so until they are standard intel core 2 duo but 2-5 months who knows?
edit: cache is not as needed in amds procs as they have an integrated memory controller

 

There are tales of the AMD Turion X2s being able to handle ram quicker, but this is not proven

check out wprime it beats a lot of core 2 duos because of the intergrated memory controller with lower latency

 

I own Turion64 X2 and have looked and benched my own! as everyone says C2D wins, no doubt, all I can say is please AMD make your next release good!

AMD does beat core duo, and their ideas are what got Intel off the Ghz drug so maybe a thank you, sorry things are not going well! Might be in order!

 

Ditto. I was blown away with some of the Turion scores.

 

I prefer the C2D, simply because of the raw performance. But the Turion X2 is a very good CPU, and should be not be put out of the picture when buying a laptop. It is a cheaper CPU, making a good choice. But in fact, in application tests, I doubt I'd be able to tell the difference between a similar spec Turion X2 and a C2D. The difference might only be apparent in benchmarks.

 

will someone tell me please.. what is the AMD's equivalent procrssor to intel core 2 duo ?? and more details please about the FSB in AMD..

Thanks

 

The Turion X2 both it and C2D are 64 bit,core duo is 32 bit but speed wise is similar to Turion X2

FSB on AMD is also called hypertransport.

 

This is completely false. All modern performance processors need cache.

 

Intel is going to release core 3 duo after penyrn that is going to have everything Amd procs had that intel did not. Prefer Intel more.

 

Yes cache is very important but obviously AMDs dont need as much either due to budget concerns or due to the way the CPU performs. The integrated memory controller on the AMDs does potentially give them a lead but unfortunately their architecture is old, they are using about the same tech they had up against the P4s and the C2Ds blow the P4s away.

 

I've got Tx2, C2D & C2 in several puters, and C2D seems faster and more efficient to me.

 

The architecture of the processor doesn't really change the benefits of the cache. Neither do budget concerns...

 

go to like reviewcentre.com or something. but the Intel Core 2 Duo beats it though.

 

Yes, but there is a law of diminishing returns. The second 2MB of cache does not give all that much of a performace boost.
Instead, http://en.wikipedia.org/wiki/Turion_64_X2
indicates the CPU-RAM bandwidth is 12.8Gb/s which is twice the speed of Intels C2Ds

 

I never said anything contrary to this. While I agree the memory bandwidth on the Turion is probably significantly faster, Wikipedia is not a valid source for this.

What I meant by my statement is that increasing the cache on a Turion will have an effect similar to increasing the cache on a C2D.

 

That bandwidth is irrelevant tho...

$ for $, C2D smokes Turion

 

actually, there is new amd cpu coming out this month and there is soon mobile one. i dunno about intel. they didn;t say anything about new stuff, only "remodeling" the current cpu.

 

Intel will release 45nm transistors CPUs...
And with July 22nd price drops ( for desktop ) and september 2nd price drops (for mobile) AMD will have to release a very nice CPU to be able to match intel's price/performance.

 

Why is it irrelevnant ?

 

intel c2d already has more bandwidth than it needs. Unless you do really specific high memory bandwidth requiring apps.

 

Irrelevant probably wasn't the most apt choice of words; it seems that it would be more apt to have characterized a 4MB cache as being too marginal to be worth the airplay it gets.

Wikipedia may not be the horse's mouth, but it's usually a very persuasive source, and oft-times tells more truth than does the old nag itself (Intel being a good case in point). With that in mind, a more pertinent link to Wikipedia would be to the discussion of caches at: http://en.wikipedia.org/wiki/CPU_cache

In particular, the graph about 1/3 of the way down the page on the right-hand side appears to indicate that, as a result of a rule of diminishing marginal returns, and depending on the particular version of "associativity" (see the Wiki article for a definition and discussion) used by a particular cache, cache sizes over about 1MB don't provide any significant improvement in performance.

Now, please keep in mind that I have no particular expertise in this area, so all I'm doing is drawing what appear to be reasonable common-sense conclusions from the material discussed in the Wiki article. With that in mind, the AMD L2 cache appears to be optimized based on the "associativity" implemented by AMD, namely, "2-way associativity" (the Wiki article only discusses the AMD implementation of its cache technology; since I don't have the time to track down any info on Intel's cache technology, I cannot say whether this sole focus is because the author(s) have a predilection for AMD, or because Intel is too pig-headed to release any info about its cache technology).

Specifically, for a cache implementing 2-way associativity, a cache size of about 512KB appears to be the optimal cache size (extrapolating from the line-graph in the Wiki article, which provides data points for only 256KB and 1MB). In other words, increasing the size of a cache using 2-way associativity above about 512KB will not provide any additional significant improvement in performance - in other words, any resources allocated to the cache over 512 KB are wasted.

Since Intel's Santa Rosa Core 2 Duo variant (for the T7300 and above) has an L2 cache of 4MB, or 2MB per core, that suggests that either (1) Intel is wasting resources for the sake of generating sales based on penis-envy, (2) the Santa Rosa chipsets T7300 and higher use direct associativity (again, see the Wiki article and the graph referred to above), and a cache-size study that uses a greater number of data points indicates that increasing cache size from 1MB (the last relevant data point on the Wiki graph) to 2MB still produces enough of a gain in performance to make the expense of allocating those additional resources worth the while, or (3) Intel has implemented some more exotic cache functions (beyond those discussed in the Wiki article) that can make economically sensible use of the larger cache size.

My under-educated conclusion from all this is that the mere fact that the Intel Santa Rosas of T7300 and above have a 4MB L2 cache is irrelevant, unless either (a) conclusion (2) above is true, or (b) conclusion (3) above is true, and my particular use of such a chip would benefit from the particular exoticism implemented by Intel.

Other than that, unless Intel is willing to divulge (and perhaps they have, as I said above, I haven't the time right now to look for such info) more details concerning their cache technology and the rationale for giving each Santa Rosa core a 2MB L2 cache, I can only conclude that a 2MB cache (1MB per core) is more than sufficient, and anything above that is a waste of precious resources (which used to be a sin in the computer world - I cut my programming baby teeth on an Atari 800 with 48K of RAM, and an IBM 5155 with 640K of RAM - anyone who thinks the Clevo 901 is a "beast" should see the following webpage for the specs on the old IBM "luggable": http://oldcomputers.net/ibm5155.html - the d**ned thing weighed 30 pounds for cryin' out loud).

Conversely, and again based on my layperson's reading of the Wiki page referred to above, AMD seems to have wasted no resources in providing the optimal cache size for its current CPUs. One can only hope that AMD's current state of embarrassment will end with a next-generation set of chips based on the same sort of economical cost-benefit maximization that will once again beat the pants off of Intel.

 

I thought with Intel both cores could access the entire 4MB L2 or is that only with the L2 of 2MB? Which if the above is correct just makes it that much worse. One thing Amd is trying to do is create scalability so as the CPU's improve you can swap them out not the MoBo or entire system.

 

L2 cache is available to both cores.

The wikipedia article you mentioned (Havent read it all) does not seem to talk about Core 2 Duo specifically. There definitely is a reason for intel to spend money putting 4MB L2 cache.

Also, the graph you describe shows an improvement in the miss rate with more than 1MB cache... However, this is not L2 Cache specifically.

Also, we were not talking about cache size, but about Random Access Memory to CPU bandwidth.

 

The intel Core 2 Duo Extreme X7800 uses 16-way set associative L2 cache:
http://i11.tinypic.com/67qd2lz.jpg

 

I do not believe that is comparable. More like an 8 X 2 thing, but I am no expert!

 

well i read in an article a while back that c2d cores share the L2 4mb or 2mb cache rather than the quicker turion way of each core having its own L2 cache

 

Then you can't really compare the two, can you?

So does the E6600.

Usually higher associativity yields better performance.

There are advantages to a shared cache. Among other things, it is more flexible in that one core can half more than half of the cache if it needs it. Another thing is coherency - if you have two separate caches, you have to do extra work to make sure they don't conflict with each other. Do you have any good sources that explain how a split L2 is optimal?

 

they dont need as much of course they need cache but how can c2d and tx2 be similair unless you do benchmarks if the turions have half the cache?

 

Because I know how caches work and why a processor needs them, and it doesn't have much to do with the architecture of the processor. It is mostly determined by the speed of the processor vs. the speed of the memory, and the characteristics of the application you are running.

 

if you say so

 

Think of the cache as a separate entity from the cpu. It's sole purpose is to make the memory appear faster. An Intel cpu requests reads and writes to the memory system (including the cache). An AMD cpu also requests reads and writes to the memory system in much the same way. How is it that a certain speedup in memory would help one cpu but not the other?

 

the cache is not as important because of the memory controller integrated in AMD's CPU's

 

If I thought it would have been useful to see you say this again, I would have scrolled up. Do you have any explanation for this comment or don't you?

 

Actually, while there are many benefits to having a shared L2 cache, avoidance of conflict is not necessarily one of them. As indicated in this article: http://etd.lsu.edu/docs/available/etd-06122007-093459/unrestricted/Prakash_thesis.pdf

at page 17, one of the downsides to a shared L2 cache is greater latency and competition for shared resources. On the other hand, as that article points out, one of the benefits to be gained is the avoidance of redundancy, as both cores can share the same data and therefore avoid the need for redundant copies in the private L2 cache used by the AMD cpus.

However, the benefit of the shared L2 cache on the C2D is not as great as it might otherwise appear because the AMD cpus benefit from AMD's hyper-transport technology and an on-die memory controller.

Basically, it appears to be the case that the C2D has to have a much bigger L2 cache to overcome some of the inefficiencies that arise from a shared cache structure; that being said, as all of the comparisons indicate, the C2D is still a better chipset than the current AMD offerings, in part due to the shared L2 cache.

What that all means is that comparing C2D to AMD is likely to be a "fruitless" apples-to-oranges comparison (pardon the pun) unless one gets beyond the size of the relevant numbers and actually attempts to take into account the different architectures of the chipsets.

So, to answer a variant of your question, namely, are there situations where a C2D with its shared L2 cache is not the optimal solution? Yes, as indicated by the discussion and graphs contained in the above-referenced article at pages 26 to 28. In the scenario described on those pages, the authors ran a memory load-latency test on a C2D E6400 (2MB shared L2), Athlon 64x2 4400+ (2x1MB L2), and a Pentium D 830 (2x1MB L2). The test was run using the lmbench benchmark test and, once the size of the array being used in the test exceeded the size of the L2 cache, the AMD had a significantly lower memory latency than did the C2D.

QED. Now, having satisfied the technical question, I should point out that I am in no wise claiming that the AMD chip is better than the C2D as a result of one limited, generally unrealistic benchmark test; as the article referred to concludes, in general the C2D is a superior chip, in part due to the flexible nature of its shared L2 cache.

 

I would expect the L2 to be dual ported. If that is the case, I don't see why competition for shared resources would be harder on a shared cache.

I wouldn't disagree with you. Architecture design is all about trade-offs. What I meant by "optimal" was more general, not optimal for any one particular task.

 

The "competition" in question is for use of the shared L2 cache. First, since each core would now prefer a cache size that is greater than 1/2 of the total shared cache, extra time must be used in resolving the potential conflict. Second, and here I am going by analogy to Intel's own published work on issues related to cache size in hyper-threading (see, e.g., http://www.intel.com/cd/ids/developer/asmo-na/eng/dc/threading/knowledgebase/20461.htm?page=3 ), where L2 cache misses and memory latencies from one thread slow down not only the thread in question, but also the other threads using the same physical processor (albeit running on different logical processors). In other words, once the first core requires an L2 cache greater than 1/2 the shared L2, and that core has a cache miss, it not only slows itself down, it slows the other core down as well; in the meantime, a core with private L2 cache that hits a cache miss is not necessarily going to slow down the other core. That is where a shared cache can become less than optimal as compared to split caches for each core.

As you say, everything involves a cost-benefit trade-off and, as real-world performance tends to indicate, the benefit was worth more than the cost in the case of Intel's shared L2 cache trade-off.

 

That isn't how a shared cache works. A thread does not "ask for" a certain amount of the cache, and the cache is not partitioned in that way. That type of conflict does not occur.

As you said before, this is for two threads running on the same physical processor, meaning the same core.

 

Brilliant! Truly Brilliant! That's why it was "by analogy." Yes, one physical processor, but two logical processors which generally, for purposes of executing instructions and accessing system resources, are treated as separate processors. In point of fact, just to bring the usefulness of the analogy home, the Intel article that I originally cited to also used for comparison a two-physical-core processor not running hyper-thread.

 

Intel Pentium IIs FTW!!!111!!!one!!1

 

And I'm saying your analogy does not appear to be valid. A single core cpu with hyperthreading is not necessarily analogous to a dual core cpu.

You can treat them however you want but that does not mean that they perform the same way.

And guess what? The graph shows that a dual core no hyperthread cpu behaves more like a single core no hyperthread than a single core with hyperthread.

I'm still not sure what exactly from that Intel page is relevant to our discussion.

 

Can we please reduce the flaming in this thread and keep things on topic.

Thanks

 

What precisely are you referring to?

 

As you wish. However, it would appear that better folks than I treat multi-processor systems and simultaneous multithreading as being functional equivalents, at least in terms of determining the performance characteristics of shared L2 cache. See, e.g., G.E. Suh, L. Rudolph, and S. Devadas, "Dynamic Partitioning of Shared Cache Memory," 28 Journal of Supercomputing 7-26 (Kluwer Academic Publishers, 2004), http://www.csl.cornell.edu/~suh/papers/jsc04.pdf


Now, to continue along the line of discussion, the article mentioned concludes, in part, that "the experimental results demonstrate that performance degradation due to sharing the cache can really be significant. For example, consider the case when running art and mcf [two benchmark tests in the SPEC CPU2000 benchmark suite] with a 4-MB L2 cache. If we execute only one process at a time, the IPC of art and mcf will be 2.1489 and 0.1719, respectively from Figure 4. If we run them simultaneously on two processors sharing an L2 cache without cache partitioning, the total IPC is only 1.0962. In this case, it is better to just idle the second processor than use it unless we partition the cache." (emphasis mine).

The "partitioning" the quoted material refers to is the authors' proposal to dynamically partition the cache between competing processors and thus, at least in 2004, when the article was written, was not yet an applied technology - it is entirely possible that Intel has adopted some version of the partitioning proposed by the authors, so that article, standing by itself, cannot necessarily impeach the C2D.

What it can do, however, is definitively demonstrate an instance where having a shared L2 cache is not only suboptimal, it is so inefficient that "it is better to just idle the second processor ...."

Of further interest is the article's summarization of certain related work. In part 2 of the article, they briefly discuss some of their earlier work on cache partitioning in so-called "time-share" systems (systems the authors describe as being used one-at-a-time by multiple, but not simultaneously active, processes). As a result of that work, they concluded that "the cache performance can be improved by partitioning a cache into dedicated areas for each process and a shared area." While not directly on point in the context of the AMD v. Intel dual-core imbroglio, it certainly suggests that there is merit as well to AMD's system of having a separate L2 cache for each processor on its dual-core systems. Moreover, it suggests that both AMD and Intel each have complementary halves of the whole truth, and that the route to truly strong performance from multiple-core chipsets will come from a blending of the two approaches.

The conclusions of the article I mentioned above are also backed up by tests run by Dmitri Besedin comparing the performance degradation associated with using each core in an AMD Athlon and an Intel C2D to run a separate dedicated thread, again with a focus on the L2 cache. The discussion of these tests can be found at: www.digit-life.com/articles2/cpu/rmmt-12-cache.html

Mr. Besedin compared the efficiency of shared and dedicated L2 cache in an AMD Athlon 64x2 3800+, where each core had a dedicated 512KB L2, and an Intel Core 2 Extreme X6800, with a 4MB shared L2. The point of the exercise was not to compare absolute performance data - the Intel did better than the AMD - rather, the point was to compare the relative performance degradation of the two chips. The results of his testing were a bit surprising, so I'll quote portions of his webpage.

The surprising bits came out when Mr. Besedin ran tests under which each core was echanging data that, by itself, would fit within the 4MB L2 cache but that, when added together, exceeded that cache - in this case, the aggregate amount of data exchanged was 5MB.

"Thus, when two cores compete for shared 4MB L2 D-Cache in Intel Core 2 processors for any access type (reading only, writing only, or simultaneous reading and writing), it can efficiently cache data, which size does not exceed 1.25 MB, that is approximately a quarter of L2 Cache (!)."

And again: "the current implementation of shared L2 cache in Intel Core 2 processors demonstrates quite a different situation [to a hypothetical ideal 2-core processor with 2+2MB L2 cache]: the first as well as the second cores reach similar mediocre data exchange rates, which are even lower than system memory bandwidth."

What Mr. Besedin's results appear to indicate is that, where one of the two cores is running a process that requires more than 1/2 of the shared L2 cache (in this case, 2MB), the competition between that core and the other core for use of the remaining 2MB of the shared cache not only slows down the first core (which it would do in any event if each core had its own dedicated 2MB L2 cache), but that it will also slow down the second core (which would not happen if each core had its own dedicated 2MB L2 cache).

Now, let us come full circle and get back to the potential relevance of the Intel webpage that I cited to earlier. The purpose of that webpage was to provide guidance on determining the correct block sizing for L2 cache in a hyperthreaded processing environment. That Intel article concluded that the optimal block size was about one-quarter to one-third of the available cache. So, we have an interesting set of disparate sources all pointing in the same general direction, which gives at least circumstantial support to the conclusion that shared cache is, as instantiated in C2D, an inefficient process that Intel has managed to turn into a workeable product by simply throwing excess L2 cache at it.

So, once again, to get back to the original topic - AMD Turion vs. Intel Core 2 Duo, and the subject of L2 cache, merely comparing published numbers for similar components of the system architecture is not a particularly good way of evaluating the topic at hand.

 

My apologies if I've offended.

 

Can someone tell me which processor does the AMD turion TL-56 correspond to for intel?

 

I don't somtimes know if you guys are talking to each other. Actually I don't know if the listening and thought is going on! But I am learning a lot. I am not going to pick sides but I am learning. So guys give a little, and teach us! I don't want to fan the flame! But here it goes! AMD (turion) is less dependent on the L2 than C2D it can access faster and has less to search! AMD is on die, why does that matter? Hmm? Faster? I almost forgot doesn't AMD have More L1 cache? Meaning less hits to L2? Go on Boys don't want to slow you down!!