AMD's Ryzen CPUs (Ryzen/TR/Epyc) & Vega/Polaris/Navi GPUs

Manufacturers have a ceiling their hardware can run at, you can only bleed so much from a stone. what you suggest then is to keep clocks low and let the users bleed the stone, so too say. AMD marketing has decided not to make the user have to bleed the stone. Now this is bad for extreme stone bleeders but good for about everyone else so since this is a mass appeal market you can not fault them at all.

 

See it this way. Brand new 7nm AMD 8 cores chips can’t compete With Old 8 cores from Intel. They simply haven’t oc headroom. 9900K play with it. Old 14nm++ destroy new AMD if ocd with equal cores. That’s sad don’t you think? Would it be even worse if Intel had refreshed same way/time as AMD?

 

then the points we are trying to make are different, no need to go further.

your point is you want to compare apple to orange, thing is intel arch will always be different to amd arch. so in general we only compare the performance.

amd's IPC lead by ~6%, while intel can have a frequency lead of up to 18%. intel wins hands down here in terms of performance in single threaded scenario.

 

"Single threaded" isn't really single threaded, fully, anymore. Even when talking about games, use of up to four cores is pretty common.

Instead, we are coming back to the old complaint of software optimizations. Sure, some tasks don't parallelize well. Because of that, serial tasks and ST performance matter at those tasks.

Moreover, we see in the game tests that when an engine is Ryzen optimized and able to scale with multi threading, AMD can do very well against Intel. When it is an older engine without optimizations, it gets beat hard.

Then there is analyzing the cache and memory effectiveness, latencies found on each uarch, etc.

Intel has prayed for development and optimizations for their hardware for decades. AMD can not and has not. I complain about Intel's unfair practices in the past, like gimping other manufacturer's hardware on their compiler, but just making the tools, distributing the tools, and giving support on how to use the tools is NOT unfair, so long as they don't do more than that. Because of this, Intel has a software ecosystem in which AMD is playing, not the other way around, nor a public, open software ecosystem where all are welcome (to a degree, although this would need broken down to complete the analogy and divulge into discussing open source in general). That includes looking at Microsoft's scheduler.

Now that AMD has gotten this far, they don't need coddled or defended on other bases. They need to go for where they will get the performance. We talk about uarch, process node, etc. But AMD needs to use this win to develop their software side of their ecosystem, without which they will always be playing in Intel's court.

Either way, tech will come hard and fast until around 2023, but especially until the latter half of 2021, assuming Intel does get to 7nm then and has 10nm on desktop, while AMD moves to 5nm, while GPUs should be on 7nm/5nm Samsung for Nvidia (7nm next year), Intel GPU on Intel 10nm/7nm/Samsung 7nm/5nm, and AMD on TSMC 5nm. That is quite a few nodes in a very short time.

3nm should be across them all (Intel 5nm/7nm) by 2023. Beyond that, III-V and gate all around FETs will be approaching their limits, potentially, as 2nm presents very BIG problems. Plus, the development costs explode under 7nm for each node, so there will be a allow down and longer ride just to recoup costs while further refining processes.

Beyond that, graphene needs a gap injected to actually be usable. We need a better interface for quantum computing, and we'll just build out servers like crazy for compute needs.

 

But you're comparing a highly refined 14nm node to brand new 7nm one... and on top of that you add Intel's OC headroom to boot.
Stock for stock, AMD compared favorably to Intel, consumes less power, is better at productivity and costs far less.
Plus, there are those pesky security flaws that Intel is susceptible to and AMD is not.

And finally, there's the issue of software optimizations.
Most games and a lot of industry software have been made with Intel optimizations in mind... that's why they perform better on Intel hw despite AMD having better uArch.

 

The problem is for the same money AMD has more cores. The winner here is performance per dollar and also over all top performance. Other than games AMD has won big time here.

Also there are other thread dedicated to Intel/AMD discussion, please use them as Intel topics posted here from now on will be considered trolling the thread!

 

amd has shorten the gap much more this time with zen2. it has amazing ipc for sure, sadly majority of software nowadays for consumer uses ram and that plays a big role in its overall performance.

with chiplet, memory latency suffers and having a big cache does help to an extent. imo it's advantage of extra IPC is offset by the latency to other ccxs and memory heavy workloads which sucks

 

Maybe latency could be improved but in the end as these are they work great. Later down the line there will most likely be other improvements.

 

This isn’t fair you put me in this box(use my or my posts as example). But I respect what you say. I will sir.

Edit. And I hope other will. I hope you see what I try to say.

 

i cant remember which video GN or HU showed the inter core latency and to other ccx latency. there was a post on amd reddit as well assuming its accurate. average latency from core 0 to say core 11 for 3900x is about as much as CFL if not less which is a bonus.

really want to see how they can improve it more with zen3 and possibly zen4

 

Im sure this has been addressed somewhere here, but ryzen has just hit its 2 year anniversary which begs the question: If its so good, why are we not seeing any good laptops with it? I would certainly have been interested in a ryzen laptop pared with a 1070, and If I had to guess AMD would even ditch bga. When I mean good laptops, I mean good quality Clevo, MSI, and Tongfang laptops that actually have good cooling and build quality. Im not saying other models with say asus or gigabyte are not bad, but lets be honest, aorus is gastly overpriced and overheating alot like razor or all these other niche laptop brands.

So have I completely missed some unknown good ryzen laptop fatbook somewhere?

 

As far as mobile, the high end Clevo's and the like are the minority of the market. AMD has gone after the market somewhat with the 2500u and 3500u but not the smaller high power market, maybe with the zen2 down the line they will.

 

Leaks, salt shaker required;


https://www.techradar.com/news/ryze...hints-at-how-quick-amds-next-gen-cpus-will-be

https://hothardware.com/news/amd-ryzen-threadripper-3000-16-core-cpu-spotted-online

Edit; The one good thing I like if this is true is that 48 and 64 cores are the WX, this might mean up too 32 core is just an active CCX of up too 2+2.

 

zen3 or zen4 memory controller back onto the chiplet with core pls thanks amd

 

I disagree. The very purpose of using the I/O chip is specific to chiplets, defeating the NUMA node problem, and standardizing latency to prevent stale data issues.

Instead, you want the UMC to have it's ability to be separate, or not go to 2:1 mode when the memory is above 3800MHz, all while also decreasing IF latency further, which may come with an increased bus width even further, used to prepare for PCIe 5 & 6, while working to solve the IF ceiling of 1850-2000 MHz, not for latency, but generally to help with higher potential clocks on the UMC above 2000MHz.

 

non sense, just have IMC on every ccx and u wont have performance issue. amd should give us the least amount of latency possible from ccx to ccx as well as memory latency.

cheap out on not giving memory access to all ccx create problems. each ccx should have direct access to memory rofl give us MOAR. single chiplet 8 core CPU = 2 ccx's, dual channel. duo chiplet 16 core cpu = 4 ccx? quad channel, no more excuse, upgrade mainstream to HEDT and destroy intel.

thread ripper and eypc can do 8 channel or 16 for all i care i just want good cpu.

 

You evidently have no clue what you are talking about in regards to these CPUs then.

IMC on every CCX means that you have a Non-Uniform Memory Architecture (NUMA). NUMA was the reason for the gimped performance on the 2970WX and 2990WX. It wasn't because of bandwidth, but rather that the scheduler for Windows did not allow for spawning beyond two NUMA nodes. That means going to a third or fourth die hurt performance SIGNIFICANTLY. It also increased memory latency whenever having to use the memory channels on the other die. If you further gave each CCX its own mem channels, you create even more nodes, breaking it into quad core nodes, all while increasing memory latency overall.

Further, going for the lowest latency DOES NOT ALWAYS GIVE YOU THE FASTEST OVERALL RESULTS! The reason for this is stale data. By the time the data gets to the other CCX, then is processed, it no longer is relevant. By standardizing latency instead of having 4 tiers of latency, depending on what is being processed where, even though slower on real terms, actually increases performance through reduction of stale data. I've explained that concept in depth previously.

Moreover, by having the memory channels centralized, you have standard memory latency throughout the product with equal access to all cores.

As to memory channels, what you actually need to discuss is memory bandwidth, which is the whole reason for quad channel and 8-channel memory, not latency. Many consumer products are NOT memory bandwidth limited, although some are.

Finally, these are good CPUs on an objective basis. It is fine wanting more, but please understand the reasons for their decisions BEFORE spouting off. Otherwise, you don't realize what you are asking, what problems it would introduce, etc.

Now, generally, I do want more mem bandwidth. But, as they move to potentially the 5nm node, throwing some low latency HBM on chip would likely be a better solution than your suggestion, as even one stack of HBM2 is around 256GBps, or a 5X increase over DDR4, while also giving a 4GB L4 type caching, all for about $60 more in cost.

But, that brings the 8-core price up to $400 for the 3700X, the 3600 to $260, the 3600X to $310 or so, the 3900X to $560, and the 3950X to $810, making the pricing a little harder to swallow for some purchasers.

For HEDT, throwing on two stacks of 4GB HBM2 in between the core dies so that each short side, if there is room, goes core dies, HBM2, core dies, you could add 8GB of 500GBps bandwidth ram, faster than the fastest 8-channel memory bandwidth, while being able to store enough for most programs without having to travel off too much, except in ram capacity limited situations.

But that is my point. There are possible solutions, but stepping back the way you suggested would move performance in the wrong direction.

 

regardless of architecture. knowing the arch and how it affects performance is just a hobby. honestly dont care that much as i simply want to have the best cpu and if amd can take whatever it takes to reach there im all good.

also i was right it is coming @hmscott https://wccftech.com/amd-ceo-7nm-navi-high-end-graphics-cards-and-4th-gen-ryzen-cpus/

let see some amd mobile GPU vs rx 3000 series

willow cove looking good too https://www.tomshardware.com/news/intel-tiger-lake-10nm-cpu-gen12-graphics,40048.html

 

Well, it was pretty obvious there are going to be higher performance sku's and lower tier sku's along with APU's using 7nm, it's all a matter of time. Why lose time waiting for what might be a long wait?

The current AMD Ryzen CPU's and Navi GPU's are well worth their asking prices and deliver great performance right now.

Why wait further for "better" CPU's / GPU's that might take a long time to arrive?

Why not get in on the action now and learn at the same time AMD progresses forward with improvements in firmware, drivers, tuning software and independently found tweaks and tunings.

It's already been a long wait.

 

not so much for waiting a long time, more to do with cost. if i get AMD rig i'll end up with more cores for sure but i'd need to buy everything new and if im gonna do that i might as well get something much better than what i have now. zen2 with it's frequency wont be much better than what i have now in terms of ST performance.

it'll make more sense for me to buy a 9900k or kf once prices dropped more and run it with 8c/8t in my laptop and wait for zen4/tigerlake for a big upgrade.

im running at 4.8ghz 6cores right now so with zen2 i'll need at like 4.4ghz which is just to be on par with same ST performance. just pointless to spend that much and no improvement.

 

Well, if you don't have a 9900k right now, then Ryzen 3700x, 3800x, 3900x should all far outperform your 6 core CPU.

Maybe not in some things, but enough to make a difference.

Of course that depends on your use, but if you don't have a use for a Ryzen 3700x, 3800x, 3900x over what you are running now, then you probably don't "need" that 9900k either.

Maybe waiting till the x590 + 5800xt + 3950x is long / short enough of a wait?

 

u know i was over optimistic back then on zen2 but if i thought about it, was too much on the plus side. double the core for same temperature only applies at optimal frequency EXCLUDING I/o die as well, while at max density of 7nm. just isn't gonna happen, so we end up with like 40% to 50% power efficiency over zen+ which is still great, was waiting for the 100% lmao.

zen4 on 5nm will bring closer to that, so thats the one im really waiting for. big ipc jump, lots of cores, low power. or tiger lake which has like 25-30% IPC over skylake, pretty big if you ask me.

 

Right now, Tiger isn't planned for desktop. Also, the IPC, I have to see to believe, but also have to wonder of Intel has to go slower or not to achieve it. If slower, then how much gain is there?

It's like Intel putting AVX 512 on consumer chips. That's fine, except very few consumer programs utilize it. In that way, it starts feeling gimmicky.

Get a 9700K and save some money. 9900K is a waste if disabling HT. Just buy it without and save like $100. It makes a lot more sense.

On GPUs, my recommendation is hold until next year for Nvidia's 7nm, amd 2d gen Navi, and Intel's GPU, although not longer than August, because if you are saving it for holidays, screw that company! That means if Nvidia does like Turing, screw them. If AMD doesn't have the big die by August and SIGGRAPH, screw them. If Intel is trying to tease at Computex and release in October or November, screw them.

Simply put, if you don't have your new GPUs out in time for back to school, you miss the boat. Period. CPU for Christmas upgrades on systems is fine. I don't complain as much on Q3 and Q4 CPU releases. But Nvidia normally goes spring and AMD by August. For CPU, I liked the second year Ryzen, with coffee in the fall and Ryzen in late spring. And I do understand the delays to the new node. But come on.

Also, considering 4K@120 screens are coming, along with 8K@60, DEMAND HDMI 2.1 support and the new DP standard!

We are on the cusp of new features and the ports are a must, not a nice to have, unless you upgrade yearly.

So, even though my 980 Ti is long in the tooth, I'm waiting.

 

This is a general warning, further thread trolling here will have consequences!

 

AMD has been on top of community interaction to find issues and resolve them quickly, here's an Update from AMD for AGESA fixes + more:

Community Update #5: Let’s Talk Clocks, Voltages, and Destiny 2
Blog Post created by rhallock on Jul 30, 2019
https://community.amd.com/community...te-5-let-s-talk-clocks-voltages-and-destiny-2

AMD Placeholder for updates on expected fixes, with the expected updates:

PLACEHOLDER: Update on WHEA Warnings, Destiny 2, and desktop idle on July 30
submitted 5 days ago * by AMD_Robert Technical Marketing
https://www.reddit.com/r/Amd/commen...date_on_whea_warnings_destiny_2_and/?sort=new

"Hello, friends.
The update is NOW LIVE - What now?

1. For questions and comments, please tag /u/AMDOfficialOpen a ticket so we can get many eyes on it quickly. "

DOWNLOAD: Chipset Driver 1.07.29.xxx
DOWNLOAD: AMD Ryzen™ Master 2.0.1.1233
DOWNLOAD: Community Update #5 Detailed Brief

Check out the detailed root cause + solutions in the pdf, download it via the link above.

 

AMD has released the RDNA ISA documents, here's an online version and an offline pdf version:

AMD RDNA 1.0 Instruction Set Architecture
Infrastructure
This document describes the environment, organization and program state of AMD “RDNA” Generation devices. It details the instruction set and the microcode formats native to this family of processors that are accessible to programmers and compilers.

Spoiler: Details...

The document specifies the instructions (include the format of each type of instruction) and the relevant program state (including how the program state interacts with the instructions). Some instruction fields are mutually dependent; not all possible settings for all fields are legal. This document specifies the valid combinations.

The main purposes of this document are to:

1. Specify the language constructs and behavior, including the organization of each type of instruction in both text syntax and binary format.
2. Provide a reference of instruction operation that compiler writers can use to maximize performance of the processor.

Audience
This document is intended for programmers writing application and system software, including operating systems, compilers, loaders, linkers, device drivers, and system utilities. It assumes that programmers are writing compute-intensive parallel applications (streaming applications) and assumes an understanding of requisite programming practices.

https://gpuopen.com/compute-product/amd-rdna-1-0-instruction-set-architecture/

"RDNA 1.0" Instruction Set Architecture Reference Guide AMD
7-July-2019
https://gpuopen.com/wp-content/uploads/2019/08/RDNA_Shader_ISA_7July2019.pdf

https://www.reddit.com/r/Amd/comments/ckrv9m/amd_rdna_10_instruction_set_architecture_is_now/

 

Good news, AMD is taking an interest in updating the BIOS of laptops to allow for Ryzen CPU upgrades (at least for socketed CPU's using PGA).

Here's the post in the "Acer Predator (Vega 56+Ryzen 2) Helios 500" laptop thread letting us know that AMD reached out to provide an updated BIOS for that laptop to allow user upgrades to Ryzen 3 CPU's:

Acer Predator (Vega 56+Ryzen 2) Helios 500
http://forum.notebookreview.com/thr...zen-2-helios-500.817796/page-61#post-10938054

 

wow that is pretty sweet news! would love to see numbers on ryzen 3000 in laptops

Sent from my Xiaomi Mi Max 2 (Oxygen) using Tapatalk

 

See:
https://www.tomshardware.com/news/amd-gigabyte-pulls-pcie-4.0-support,40085.html

Gigabyte Pulls PCIe 4.0 Support From Pre-X570 Motherboards

 

If AMD sends him the updated BIOS, I'm definitely going to get a Zen 2 at some point with faster speed and low latency RAM

 

DUDE! u gotta do a complete in depth review of that mobile form factor rocket for the community here

 

I am a bit concerned, that is as it is now over a month since release and the flagship 3900x is still out of stock. We have yet to see the 3950x or any official news on the tr3 offerings.

 

The 3900X has had at least one re-up since release and that was sold out in minutes like the original.

The 3950X, although they messed up on messaging at the events leading to release, like E3, is not released until September. So it is too early to worry on that.

For TR, they did not give a firm release window. They want to target Q4, likely due to Intel's HEDT release of Cascade-X, but might slip to Q1 2020. This is likely related to potential demand for Epyc, especially after seeing those reviews and the strong demand for the mainstream chips.

The 3600, 3600X, and 3800X are all in stock. The 3700X was bought out and is being resold at insane premiums, costing more than buying a 3800X.

So just give it time to cool down and supply to equalize. Also, either plan on purchasing your TR upgrade immediately or potentially having to wait a couple months for supply!

 

I will wait till the reviews settle out. The 32 core peaks my interest but I want to be sure it scales well and not like the WX chips did.

 

Seeing the 21% uplift in multi core performance on Epyc, plus the I/O core standardizing memory latency, plus simplifying the latency by forcing all CCX to CCX through the I/O die (see Anandtech's Epyc article for that latency discussion), there is no way it has the regression. Microsoft sees the chip as a single NUMA node instead of 4 nodes now. The scheduler no longer shifts around tasks fighting for core 0 either, so no need for core prio anymore.

Basically, everything that effected the WX chips is now fixed. And if you doubt memory bandwidth can handle the core count, look at the 64 core Epyc. It will have the same amount of memory bandwidth per core as the 32 core TR.

It's fine to wait for reviews, but just watch them quickly because I believe there will be large day one demand.

 

So long as the 32 core is a 2+2 ccx configuration. It is possible it could be 1+1+1+1 ccx where then there are memory issues like the WX. As I said I need to wait and see as they are not giving any info out.

 

No, that is impossible! The memory controllers are on the I/O die and are not tied to a specific CCX. There is no extra hop. There is no limited access. It is shared access by all CCX. No CCX gets any priority to any memory channel!!!

Edit: Here is more info on the design-

https://www.servethehome.com/amd-epyc-7002-series-rome-delivers-a-knockout/4/


https://www.anandtech.com/show/14694/amd-rome-epyc-2nd-gen/2


https://www.anandtech.com/show/14694/amd-rome-epyc-2nd-gen/7


https://www.servethehome.com/amd-epyc-7002-series-rome-delivers-a-knockout/6/
That one shows the topology as seen by the system, with ALL memory as a SINGLE DOMAIN!!!

Edit 2:

This explains a bit on how you can set the NPS modes on the new Epyc CPUs. The important part about it is to read the quote from the AMD engineering team on accessing near or far DRAM channels on the I/O die, where the nearest channels are 6-8ns, second closest are 8-10ns, then the range for the two farthest channels is 20-25ns (closest of the far channels likely 20-23ns and the farthest of the far channels 22-25ns). But, it is still seen as a single memory domain, so a UMA instead of a NUMA unless told to go into a NUMA type mode.

But, even with that, this added latency going between the near or far channels of only up to 15ns, with the total range of delta mem channel being 19ns, you do not get the problem of nearby mem being in the 60-80ns while the far mem channels would be 180-240ns and two dies ALWAYS having the 180-240ns to read from memory.

" In NPS4, the NUMA domains are reported to software in such a way as it chiplets always access the near (2 channels) DRAM. In NPS1 the 8ch are hardware-interleaved and there is more latency to get to further ones. It varies by pairs of DRAM channels, with the furthest one being ~20-25ns (depending on the various speeds) further away than the nearest. Generally, the latencies are +~6-8ns, +~8-10ns, +~20-25ns in pairs of channels vs the physically nearest ones."

https://www.anandtech.com/show/14694/amd-rome-epyc-2nd-gen/8

 

Flow charts will not convince me. Actual Threadripper white paper or better yet tests of the silicon. Even the Epyc flowchart shows each of the four dual channel ram paths to the I/O chaplet closely tied to 2 ccx units.

So I am not convinced. In fact I am even more confused. Now they may have lowered latency and hop delays but they may still be there. Although I do not see it, to save money, the 16 core could even be a 1+1+1+1 ccx but I doubt they would risk crippling the chip against the 9-3950x

Edit; I also believe AMD should not NDA TR info. I do not expect the TR to be as powerful clock for clock to the Epyc but it would alleviate confusion for HEDT consumers.

 

So, more information will come from Hot Chips in 2 weeks. That is where the deep dive is scheduled.

Now, let me explain what is going on a bit more. AMD has, by default, the memory controllers set to Unified Memory Architecture, with the system seeing all controllers as 1. But, there is the ability, at least for Epyc, to break that UMA into four NUMA nodes, with them seeing each controller as its own node (with the two closest chiplets being part of one node).

There is still variable latencies for each of the four controllers. But with them all centralized, and since doing a memory call, regardless which CCX is doing the memory call, requires the same latency to go to the I/O die for each CCX, then the latency variance, depending on which memory controller must be accessed, is reduced to 25ns for travel on the I/O die at the most, and 6ns at the least. This greatly reduces the overall latency to do a memory call for the farthest latencies seen on the WX processors, while increasing the smallest latencies on the WX processors. What that means is, under my theory of stale data being a huge part of the problem on TR 2970WX and 2990WX, that the memory calls will be, for the most part, standardized moving forward.

Now, because of the added latency for the smallest memory latencies, they doubled the L3 cache. That actually slowed down L3 cache calls. But, it also reduced the number of memory calls. Because it reduced the number of memory calls, it overall enhances the performance of the CPU, which is efficiency through inefficiency.

Now, why I hope they do all 4 controllers instead of just 2 controllers is so that each potential "node" has a nearby memory controller for the lowest possible latency, while having the average latency on memory calls equalized. It also allows, potentially, for each of the four memory controllers to clock faster or be stressed more because at max you have 2 ranks per controller (4 ranks with high capacity memory like the 32GB DIMMs with 4 ranks) instead of 4 ranks (or 8 ranks if using high capacity DIMMs like the 32GB with 4 ranks). This would reduce the stress on each of the controllers, allowing for, potentially, better clocks, although this would need tested. AMD says each controller, by default, is set to interleaving, meaning the writes and reads are alternating which controller gets hit. But this also means that you would have to use the full I/O die of Epyc for TR, which means they would fuse off half of the PCIe, which seems wasteful for the I/O dies.

Now, for Epyc, it is actually the 1+1+1+1 CCX that is listed as the top 16-core SKU, listed with the most cache. If they did that for Threadripper, it would quadruple the L3 cache on the chip while likely only using the top 2 cores per CCX, which also spreads out the heat even further allowing for higher clock speeds. Where that would hurt performance is in lightly threaded workloads where you would need to go to the I/O die to another CCX node for anything requiring more than 2 cores. So for heavily multi-threaded workloads, the L3 cache would be a huge boon, but you get a hit on lightly threaded stuff. For server chips, it explains exactly why the top 16-core is setup with 4 dies, as servers are often meant to have heavier multi-threaded workloads. But, it is unclear about the benefit for a workstation (although I'm sure AMD has tested it, whatever decision was made).

I see 4 dies not as a way to save money, rather as a way to spread out the heat and increase the cache size of the workstation chips, while also using chips where one core was damaged or whatever. You would still need those remaining two cores per CCX to be able to clock FAST! But, spreading out the heat that much would also mean they would likely clock significantly faster, which could make up for some of the drawbacks.

I'm sure we will see more information on TR as we approach the launch.

 

AMD released the Epyc Horizon Event in full with improved audio (no echo), and it's much easier to listen to than the previously posted 3rd party coverage:

AMD EPYC™ Horizon Event - Full Show
AMD
Published on Aug 9, 2019
AMD EPYC™ Horizon event full run of show Aug. 7, 2019. For more information including endnotes, please visit: https://www.amd.com/en/processors/epyc-7002-series


bgtubber 2 hours ago
2:08:36 "You came for this." <== Continue from here for Lisa's closing with Google.

Dennis C 54 minutes ago
"Great presentation, great closing statement by Dr. Lisa Su at the end. AMD EYPC is the new standard."

 

Epyc;

 

This man is a benchmarking demon! 900+ benchmark runs over 3 16 hour days for this comparison review of the 3900x and 3600, it's nice to see Ryzen 3 / Zen 2 has caught up close enough to Intel in the gaming benchmarks so as not to matter enough for most of us to care about it

Ryzen 5 3600 vs. Ryzen 9 3900X vs. Core i9-9900K: GPU Scaling Benchmark
Hardware Unboxed
Published on Aug 10, 2019


Linus gets animated with excitement about AMD's Rome launch, after seemingly at odds about his Intel Sponsorship losing it's luster due to this bad timing - even earlier within this show - Linus goes gaga over Rome. [Intel isn't even in the competition any longer, Enterprise]

Userbench CPU score DRAMA - WAN Show Aug 9, 2019
Linus Tech Tips
38:45 AMD EPYC 7002 Rome delivers a knockout
42:00 AMD stock analysis?
45:25 AMD EPYC technobabble

 

The new AMD Epyc single socket CPU's have so much built in single socket performance it's outperforming 2 socket systems - the "standard", but given the higher than 2 socket system performance coupled with the much lower price points, Lenovo thinks it's time to bring out a range of 1U and 2U servers using the new AMD EPYC 7002 "Rome" family of processors.

These might be good choices for and perhaps applicable to home (garage / closet) service as much - or more - than datacenters. ServerAtHome seems to think so as well, both are included below:

Lenovo ThinkSystem SR635 Video Walkthrough
Lenovo Data Center
Published on Aug 7, 2019
The Lenovo ThinkSystem SR635 is a 1-socket 1U server that features the new AMD EPYC 7002 "Rome" family of processors. With up to 64 cores per processor and support for the new PCIe 4.0 standard for I/O, the SR635 offers the ultimate in single-socket server performance in a space-saving 1U form factor.

In this Lenovo Press walk-through, David Watts and Russ Resnick take you through the server and describe the major components.

To learn more about the server, check these resources:
* Datasheet: https://lenovopress.com/ds0099
* Product guide: https://lenovopress.com/lp1160
* Interactive 3D Tour: https://lenovopress.com/lp1182


Lenovo AMD EPYC 7002 Servers Make a Splash
Patrick Kennedy, August 11, 2019
https://www.servethehome.com/lenovo-amd-epyc-7002-servers-make-a-splash/

Here are some images of the 1U (thin) profile server, and the article continues with images for the 2U (double height) thick server.

Spoiler: 1U images...

Here's the walk through by Lenovo for the 2U (double height) version of the new AMD server, for applications where more internal storage and/or more PCIe slots are required:

Lenovo ThinkSystem SR655 Video Walkthrough
Lenovo Data Center
Published on Aug 7, 2019
The Lenovo ThinkSystem SR655 is a 1-socket 2U server that features the new AMD EPYC 7002 "Rome" family of processors. With up to 64 cores per processor and support for the new PCIe 4.0 standard for I/O, the SR655 offers the ultimate in single-socket server performance.

In this Lenovo Press walk-through, David Watts and Russ Resnick take you through the server and describe the major components.

To learn more about the server, check these resources:

* Datasheet: https://lenovopress.com/ds0103
* Product guide: https://lenovopress.com/lp1161
* Interactive 3D Tour: https://lenovopress.com/lp1183

 

put memory controller back onto the chiplet, every chiplet. or somehow reduce memory latency all together that'll give us the lowest latency.

 

My understanding is in order to have the over 8 cores per CPU they need this in order to increase the CCX count on AM4's and also TR3. I will need to see how this performs on the TR3 before claiming they need to go back in order to go forward.

 

Updated DRAM Calculator + New guide to tuning DDR4 for Ryzen 3 from Hardware Unboxed, great as usual:

How to Manually Tune Your DDR4 Memory For Ryzen
Hardware Unboxed
Published on Aug 11, 2019
DRAM Calculator: https://www.techspot.com/downloads/71...
Thaiphoon Burner: http://www.softnology.biz/files.html


It looks like AMD is just as serious about the Radeon group jumping forward as the Ryzen / Epyc performance jumps:

AMD Radeon Community Update: More Control Over GPU Power and Performance, Enhanced Thermal Monitoring, Maximized Performance
Blog Post created by mithun.chandrasekhar on Aug 12, 2019
https://community.amd.com/community...nced-thermal-monitoring-maximized-performance

AMD Radeon Community Update: More Control Over GPU Power and Performance, Enhanced Thermal Monitoring, Maximized Performance
Submitted 13 hours ago by AMDOfficial Official AMD Account
https://www.reddit.com/r/Amd/comments/cpdjrh/amd_radeon_community_update_more_control_over_gpu/

amd_mythun Radeon Product Management 12 hours ago
"If you guys have any other related questions...fire away!"

Lots of interesting content in the reddit thread...

 

Get out your salt shakers;
http://www.translatetheweb.com/?ref=SERP&br=ro&mkt=en-US&dl=en&lp=JA_EN&a=http://blog.livedoor.jp/bluejay01-review/archives/55705838.html

https://browser.geekbench.com/v4/cpu/search?utf8=✓&q=amd+sharkstooth

Edit compare to a 2990wx;
https://browser.geekbench.com/v4/cpu/14286239

 

That score seems possibly legit. Check out the ST on the 3700X or 3900X for comparison.

Then remember it is on Linux. Our 1950Xs can hit very high scores in Linux. So if you estimate 15-20% improvement by generation and look at it being a Linux score, it does seem fairly reasonable. We'd need to use the mainstream chips to estimate boost frequency also, which is higher, while taking into account that windows has gimped gb4 performance.

I forgot what my recent gb4 in windows 10 was.