C2D Hyperthreading?

Does anyone know if the return of hyperthreading will be extended to C2D on socket 775/P or is it pretty much restricted to next-gen socket 1333 cpus?

 

I'd say no to C2D. Since it will be on their core i5 which looks to sit in their "mainstream" lineup in terms of pricing, I would hardly doubt they would put it on their C2D.

 

Socket T (LGA 775) is mainly for desktops and its life is already ended. No new C2Ds will be released for it and no processor for that socket will utilize HT. There is no LGA 1333 that I know of, so I assume you mean LGA 1366. HT has returned in the shortly lived Socket B (LGA 1366) w/ Ci7 but that is also at the end of its life. The new desktop line with HT will be LGA 1156 for the next batch of Core i3/5.

edit: Intel might not be abandoning Socket B quite yet, seems like the Core i7/i9 might live a bit longer but no integrated GPU.

 

C2D design would simply not benefit from hyperthreading which is the reason its not there.

 

fair enough, thanks guys

 

Socket P for laptops is on its last legs as well.

 

Nope, no Hyperthreading on Core 2. Properly implementing it in the architecture would have set Intel back many months from its original release date.

1366 is a long way from dead.

 

Wrong HT would NEVER have been in C2D due to its short pipelines. No if and or buts about it.

 

Where did I state anything differently?

Adding length to the pipe, enhancing the caching subsystem to feed a higher number of active execution units (Hyperthreading is essentially all about putting the idle units to work, increasing throughput), and building the system around the Quick Path Interconnect would have dramatically increased Intel's timeframe to develop Core 2, if said tech was present. Not to mention cost-effectively producing the chips (at the time) on the 65nm process. Core 2 was Intel's return to execute performance lead and Nehalem (with the superior memory and inter-core communication, QPI) was the nail in the coffin for AMD's server marketshare with the Opties that rode on the slightly better Hypertransport (compared to Intel's front side bus).

 

It's not that simple. On the P4, HT helped a lot but on Nehalem(Core i7) it helps EVEN MORE than on P4.

The point for HT(Intel's term for SMT) is about increasing performance via utilizing the otherwise idle execution units. But on the P4, both the negatives to HT and positives to HT were there.

P4 was so bad in certain aspects that HT was merely a tool to keep the CPU acceptable. It reduced instruction latencies that were critical and were TOO SLOW to acceptable levels.

HT on P4 was "taking out the bump on the road" while HT on i7 is "making a highway out of a street".

Take a look here how well HT works on the i7: http://www.solidmuse.com/2008/12/core-i7-to-hyperthread-or-not.html

"In days past, with the old Intel Pentium 4 cpu architecture, the conventional wisdom for the best core SolidWorks performance was to disable hyper-threading in the system BIOS."

"Based on the results I see above it would appear that hyper-threading does not hinder core SolidWorks performance. For those areas of SolidWorks that take advantage of all the threads available for processing, hyper-threading looks to offer a very nice performance advantage."

Huge difference in opinions about HT between the two isn't it?

That's called Nehalem(aka Core i7 aka/Socket 1366/1156).

The problem with enabling HT is while is easy on the die size it takes a LOT of development time to make it work properly.

 

You stated "Properly implementing it in the architecture would have set Intel back many months from its original release date." What you posted is simply NOT true. C2D architecture was NEVER intended for HT. Intel did not even consider HT when designing it due to its short pipelines.

 

What do your post have anything to do with this thread????

 

that hyperthreading is useful on the current platform, and the next version of core2duo, a.k.a. the corei5 could easily have hyperthreading, as the next version of the core2quad, the corei7, has it.

and the chance is big that this is what the op wanted to know. if the next core2duo, namely the i5, will have hyperthreading. a the 'next' core2quad, has.

 

I'm trying to answer everybody plus telling you its not about pipeline length that determined whether Core 2 would have HT or not. In any way, the 14 stage pipeline Core 2 is more suited to HT than P4 did. They didn't implement it because the design goals of the teams were different, and radical changes like that are usually done with a overhaul, like in the case with Nehalem.

And the above is true. SMT is easy on the die, and hard on development.

 

Since you are so adamant that its due to "short pipelines" that it wouldn't work well on Core 2, let me tell you this.

The design goals on the P4 was high clock speeds and (very)aggressive speculation. Because of the extremely high number of pipeline stages, instructions would sometimes take too long to go from one chip to another. To counter that, the designers added along with aggressive speculation, a feature called Replay. Replay would be a "dumb" seperate pipeline executing along with the regular pipeline that would try to recover from a failed speculation. The problem with Replay was that it sometimes took up execution resources unnecessarily which is bad in situations when it needs resources(for example HT!).

Core 2 is
-wider
-less penalties like Replay
-balanced, so resource hogging tech like HT won't produce such negative effects

Nehalem, a largely Core 2 derivative processor with 16 stage pipeline, achieves an average of 20% gain on most server applications, while with Pentium 4 it was so horrible that most server users turned it off.

To the OP: No you will very likely not see a common, LGA775 Core 2 with JUST HT enabled. It's a waste on Intel's part.