FSB 800Mhz downclocking with T9900 based on FSB 1066?

Hello, everybody

I actually have an Acer 5315 (GL960/965 chipset the FSB limit is 800Mhz) that I upgraded from Celeron M530 to a Merom based Core 2 duo 7500 2.2Ghz 800Mhz fsb. It work really fine and stable.
I saw that some of you succeded to upgrade it to the T9500 2.6Ghz which is an Penryn based proc with an 800Mhz FSB too. (I was astonished, because in the Bios upgrade readme file, it is explained that the compatibles procs are Merom and Merom-lite... so anyway)

I would like to know what should happen if we put an T9900 3.0Ghz which is an Penryn too but should work on a 1066Mhz FSB???

Should it work at an downclocking speed of 2.3Ghz instead of 3.0Ghz because of the 800Mhz FSB upper limit???
Or, not work at all?

 

It won't work - the 1066 MHz FSB CPUs will not downclock to 800 MHz FSB, and the system will simply not boot.

 

Cross posting is against the forum rules your other thread have been deleted.

Johnny T - NBR Moderation Team

 

See Theory: Using a 4-series penryn (T9400/T9600) on a Santa Rosa systemboard

 

Yes you're right, I thought by after it's not a specific question for the acer computer.
Sorry

 

Did you experience that?

If you remember, which chipset it was? And which CPU?

Thanks

 

Thanks Nando4 to show me this topic. Really interresting.
A little bit difficult to follow for me.
First because of me language skill :rolleyes2:
Second, for moment I'm even not able to find where is the ICS's clock generator in my computer (perhaps under the keyboard, but not near CPU, memories...). I read some Bios readme file where it write a ICS9LPRS365, but I'm really sure for moment, I should open all my computer and for moment... I'm a little bit lazy

Ok, anyway.
So, if I follow your mind, you suggest to overclock the FSB from 800Mhz to 1066Mhz, in order to let my chipset "communicate" with the CPU external bus???

 

Suggestion in the overclocking post is:

1/ T9900 cpu is pin-compatible with your T7xxx cpu
2/ To get it to boot, likely requiring new microcode in bios (bios modding)
3/ If can get it to boot, will be 800Mhz FSB
4/ needs overclocking to get it to 1066Mhz FSB

Moral Harzard, in the same thread, has done some crazy high overclocking with his T7500, so consider going down that path before investing in a T9900. Without knowing your PLL, you can check the TME_READBACK data with setfsb to see if your PLL is TME-locked.

 

Realistically, saebasan, it's probably not worth the trouble. Just stick with the T9500, which is way more than powerful enough for anything you need to do anyway.

 

Ok, it seems the bios is able to handle Penryn base CPUs, some persons was able to use T9300 & T9500 on it.

I tried to switch the TME bit which was enable in my case (so no overclocking avaible) .
When I launch SetFSB, it show me the message "PLL ID Error", but mine should be ICS9LPRS365, and I choosed ICS9LPRS365BGLF in SetFSB. It enought/right?
So with SetFSB Diagnosis, I clicked on "GetFSB", first I changed the "PCI2 output" to 0 and clicked "Update" (system don't freeze), second I changed TME enable to 0 (don't freeze too). But when I click on "Apply", SetFsb show me "#error 19" and desapear.
Finally when I launched back SetFSB, the setting is still "0" on PCI2 but not on TME (returned to "1").
Is it correct? So in this case the next step should be to connect physically the TME/PCI2 pin to GND, right?

(If yes, I will make first some test on my T7500 with SetFSB)

Regards

 

Good - appears then the 0 to disable PCI2 confirms it iisn't used by the system, so yes, can physically connect the TME pin to GND to allow setfsb overclocking AND system will work OK afterwards. See method 1 here for instructions. If doing very high overclock like MH is, T7300-2.0Ghz 200@10x to what I believe is 2.826Ghz [email protected] (enable IDA in rmclock to enable 0.5 multipler), consider too using spd_tool or Thaiphoon Burner to increase CAS latency for RAM stability to what the parameters would be for 800Mhz operation (eg: CAS=6).

If successfully overclocked, please report to [email protected] so he can add the ICS9LPRS365 (Acer 5315 with hardware modification) next to to his list of system with successful setfsb overclocking.

 

T9300 and T9500 aren't a problem. They use 800MHz FSB. It's the 1066MHz FSB CPUs that don't work on Santa Rosa.

 

Thanks OK

My memories are 800Mhz ready and the CAS 6 is already in it. Normaly the overclock from 667Mhz to 800Mhz of the memory slot should be detected either by the Bios or by memory modules themselves. No?
Still should I change configuration in the memory modules???

Before, I will specifically look for my clock generator's datasheet. Just in order to be sure of the pin location on the chip itself.
(And find a fine soldering iron for accurate work)

Yes sure, I will report if it work till the end... we can be sure of nothing

 

System will bootup and use RAM timings in the spd_table for 333Mhz operation. Higher O/C will mean 333Mhz table will need to have CAS=6 entry like the 400Mhz spd_table has. Otherwise you'll hit a overclocking wall due to RAM instability.

Datasheet is a good idea. If it's a 64-pin TSOP ICS PLL as shown here, then Pin4 is highly likely to be the TME/PCI2 pin as shown for two previous ICS PLLs in that same post.

 

OK,
I checked many things today.
I think I will create a differant thread... I explain why

First I tried to pinmod my T7500 from 800Mhz FSB to 1066Mhz (just a test to see what happen). So I connected pin B23 (BSEL[1]) to B24 (Vss O just next this pin), in order to get all pins BSEL[2,1,0] at 0,0,0 for 266Mhz frequency selection (as write in the PM/GL45 chipset datasheet, even if mine is a GL960 ).
No screen, no bios, no boot. It don't work by this way at 1066Mhz.

Second I completly opened my computer today, and the clock generator is under the keyboard
And surprise , the chip isn't an ICS9LPRS365 BUT a Silego SLG8SP510T (not has write in the Bios' readme file of this f****** maker, euh sorry)
Ok, so in SetFSB the nearest choice is SLG8SP513V, I tried this, click Getfsb, and no error.
But I still not able to config my clock...
Finally I downloaded the datasheet of this chip, and it seems don't have TME. (no overclock lock??? lucky or not lucky ??? That is the question)

Is it possible?
So why could I not change the clock speed?

 

It does have a TME pin, just the datasheet does not show where it is.

Look at Control Register 9 in the datasheet, bit 6 is reserved.
That bit is the TME enable value and as you can see the bit is read only.

use setfsb to read what value that bit is, if it is 1 then you could try to change it to 0 with a hardware mod.

I believe that your TME will share the PCI2 pin, although it may not.
If you really want you can just try to ground the PCI2 pin and see what happens.

 

this is me quoting me from this:
http://forum.notebookreview.com/showthread.php?t=394367&page=2

where you can see another user with a simmilar PLL and you may get ideas from that thread.

 

datasheet for the PLL which I found here doesn't appear to support allowing programmable output. In which case would need to set FSb pin (pin 57 on TSSOP package) to GND to overclock from 200 -> 266Mhz. This means disconnecting that pin/track from the rest of the system, as the FSb signal appears to be a mirror of the BSEL signals going into the CPU. So want cpu to receive BSEL for 800Mhz, while you'd be setting the PLL for 1066Mhz operation. (see link in my sig if wanting more description on this).

For this to work successefully you'd either need very timing tolerant ram, or CAS=6 written into the 333Mhz spd_table using spdtool or thaiphoon burner. Thaiphoon is really easy to use. A 800Mhz FSB runs the RAM at 667Mhz (333Mhz table). Overclocking at 266/1066Mhz FSB would have the RAM running at 887Mhz, so needs to slow the RAM timings with CAS=6 for the faster operation.

 

The datasheet just doesn't show you the regesters, it says "reserved".
Some of the reserved regesters are the programing registers, the PLL does allow programing but silego don't tell you which registers to use.

Edit: silego did have a datasheet of a very simmilar PLL showing where the m/n programing registers are but now silego has removed the PDF, I will try to find it again.

here is the silego site to find all of the PLL datasheets:
http://www.silego.com/ftg.shtml

I'm not having any luck finding it but I did download it before and I think it's on my other HDD so tommorow I will check if I still have it and if I do I will upload it if you wan't.

 

Thank you Nando4, I found effectivly the same description pic than you. I came to the same hardware solution than you, as FS(a,b,c) and BSEL(0,1,2) frequency code are similar. (But I prefer use it as the last chance solution... )

And thank you moral hazard, I downloaded yet the same pdf than you, read quickly that there is some programmable register inside.
Yes if you find a more complete datasheet, I'm interested in it.

Perhaps should I ask to the SetFSB programmer if he can use theses informations?
(I think he's Japanese, no? I'm in Japan right now)

 

Yes - Abo is Japanese. Email him on [email protected] asking politely to add support for your PLL. He'll want the PLL datasheet to work from and a screencapture as follows within setfsb:

Select SM Bus read/write=Auto[PLL parameter]
1. start SetFSB.
2. select the clock generator to "PLL diagnosis".
3. click "Diagnosis" button.
4. click "Get FSB" button.
5. click "Capture" button.

Send "Diagnosis" screenshot of the setfsb capture folder.

 

here is a very nice datasheet:
http://www.silego.com/resources/pdf/xSLG505YC264Cr07_04132009.pdf

It show the TME pin, which does share the PCI2 pin.
It also shows where the m/n programing registers are.
I think it also has the same number of pins as your PLL.

Edit:
another nice datasheet:
http://www.silego.com/resources/pdf/xSLG505YC264Br10_08042008.pdf

this shows that silego likes to use the same registers to do the same things, like register 15 on both datasheets is a programing register and so on...


another:
http://www.silego.com/resources/pdf/xSLG505YC64Dr11_02132007.pdf

another:
http://www.silego.com/resources/pdf/xSLG505YC64Lr10_02152007.pdf

It looks like these PLLs and your PLL are very simmilar to each other.
You can compare the datasheets to guess which reserved registers on your PLL are the programing registers.

I think it will be registers 15,16 and/or 22,23.

 

Thanks so much moral hazard.


But all the datasheets you find out are for SLG505YC series. And have effectivly the TME pin.

However, the one I'm looking for is SLG8SP510. We found yet one datasheet at this address http://www.datasheetdir.com/SLG8SP510+Clock-Synthesizers
Unfortunatly, I have the one clock generator in the world which don't have the TME pin. (T_T)
I guessed perhaps you knew a more complete datasheet for the same chip.
Because the pdf here is a little bit light.

It's write in it, at page 8/24 that the SLG8SP510 can be read/write by SMBus. (So programmable)
But, at page 10/24 the Control Register; bit [5:7] are "Reflected the value of FS pin sampled on power up", and are just readable... (T_T)

I will make some test... without hope
(Anyone know what is iAMT enable mode?)

 

Your clock generator does have the TME pin, silego doesn't tell you which one it is. But you can assume the TME pin is the PCI_2 pin.

Also If you look carefully at your datasheet you see that bit 6 of byte 9 looks much like a TME register value. You can see it's read only.
can you check with setfsb the value of that register?
If it is 1 then you need to modify the TME pin to set the value to 0.

sorry, I can't seem to find a more complete datasheet.

It doesn't matter what bit [5:7] are because you don't program them.

the registers to program are the "m" programing register and the "n" programing register. I believe they are registers 15 and 16.

So if you make the TME value 0 then you can write to the m/n programing registers and tell the CPU exactly what frequency to run at. Just use the closest available PLL in setfsb for this.

So your choice is to try to connect PCI_2 to GND and then try setfsb again.
Or just do what nando4 said before.

Edit: It would be nice if you could take a good photo of your PLL so we can see the tracks comming from it and what they lead to. Hopefully the tracks will lead to resistors, then the PLL mod would be more simple.

 

How to program the PLL:

If you wan't a 200mhz fsb then change control register 15 to 11001000.
if you wan't 201mhz = 11001001.
and so on...

It is just a binary representation of the frequency.

But you won't be able to change the bits in constrol register 15 or 16 unless TME = 0.

If TME = 1, the registers will act as if they are read only.


Edit: The programing of the PLL is not as straight forward as I have described but it is close enough.


Please tell me the value of bit 6 of byte 9.
Also can you tell me the value of byte 15 and byte 16.

 

Ok, I followed you explanations. Thanks.

I launch SetFSB with a bit differant setting (SLG8SP513V and not 510T) but it seems to work correctly. No error message, and it give the right frequencies I use.

So I switch to diagnostic.
I changed the bit2 of register2 to 0 (PCI2, it was set to 1). The PC don't freeze, and the bit stay to 0
I continued, I tried to changed the bit6 of register9 to 0 (TME which is set to 1), impossible to switch it, the bit don't change. (And it's logical if we follow the datasheet, because this bit is done as read-only and reserved)
Finally I tried to changed the value of register15 & 16, which was all on '0' (each bit). They are able to memorate the value a applied to, but it changed nothing in term of speed (perhaps normal if the pin 4 we expect to be the TME as all the other generator is set to 1). There two registers too are done as "reserved" in the datasheet.


I sent a mail to Abo from SetFsb, with screenshots of the soft and datasheets. He answered me really quickly, thank to him.
But unfortunatly, he simply said me like that "Hmm..., LG8SP510T doesn't have the function that change FSB with the software. To my regret, I can not support it."
I think he really have an high experience of readding these kinds of datasheets. So I trust him, evenif I still would to make him lie (a little bit, just for my computer )

 

Abo, like myself, has read the datasheet looking for M/N registers, TME pins and found no mention of either. Moral Hazard is suggesting that the manufacturer has NOT disclosed that info. I can't say if that is true or not other than to say that the details of the config registers you point out so far suggests the PLL appears to clone the ICS PLLs in it's functionality.

On a ICS PLL, the status of TME_READBACK tells us if TME is enabled. This is register 9 bit 6. If set to 1 it means no overclocking TME-mode is active. It can only be read from. Yours is set to 1 (TME enabled)

Writing a 0 to the register 2, bit 2 disables PCI2 Output. PCI2 pin is shared with the TME pin after post. Since your system is fine after that write, we can assume it's not using pin4 to provide PCI2 signal. I would advise proceeding to GNDing TME/PCI2 pin (pin4), as is done on a ICS PLL, to remove the TME lock as shown here. Easiest if there is a resistor attached near it that you can lift and run a tiny wire from to the inner (PLL) side to a GND point, then check the TME_READBACK status after doing so. With a resistor present it's easy to reverse the process if need be.

Might be helpful too if you can paste a screeshot of the PLL config registers from setfsb.

 

Yes, it's right.
It write too that the SLG8SP510 is a CK505 clone and should have the 64pin TSSOP same pin configuration.


Here the 'clearest' pic I was able to take...



And here in red what we suppose to be the TME (I'm not sure if I can fint a resistor around), and at other side still in red the FS_B which should let me change the FSB too. (I thought perhaps to connect on GND with a little jumper to be able to select either 200Mhz or 266Mhz )
In green an resistor which could be connected to the pin FS_B..?

 

This means that registers 15 and 16 are not the m/n programing registers. If they were then the values should not change until you set TME = 0.

I will try to guess which other registers could be the m/n programing registers, probably by tomorrow.

Until you find the m/n programing registers your only option will be the FS_b mod.

"reserved" doesn't mean anything, I have read about one person who changed a reserved bit from 1 to 0 ( it turned out the reserved bit was the TME bit) and it allowed overclocking. Just because a bit is reserved doesn't mean the bit is useless, it just means that silego doesn't wan't to tell you what it does.

 

You can check with a digital multimeter to see if the resistor is connected to pin FS_B

 

saebasan, it seems I ran into the same brick wall your now facing. AFAIK some of the Silego chips don't support programmable overclocking but in order to provide ck505 compatibility provide the registers even though they don't do anything useful. It's still worth a try as moral suggests but there is also a chance they are just dummy registers.

For instance IINM if TME is enabled (no overclocking allowed) as shown by bit 6 of register 9 then you should not be able to set bit 7 of register 17 CPU PLL M/N Control enable to 1. On my PLL I can set this to one even with bit 6 of register 9 set.

Same goes for bit 7 of register 14 Frequency Select Source, AFAIK I shouldn't be able to set that register bit if TME is set, but I can.

I really hope TME exists and it does work for you as being limited to an FSB frequency table change is not so flexible.

P.S. Is this the datasheet your looking for?

 

Ok, I understand now.
The m/n programing registers must be 15 and 16 for your PLL, but as 0.0 pointed out, they are probably just dummy registers.

So that is why the values are all zero for those registers, and that is also why you can change the values with no results.

My only question is how does setfsb support that other silego PLL?

Edit: If you like taking risks you could try to connect PCI_2 to GND and see what happens (make sure you disconnect it from VDD first).

Well your best option now is to just do what 0.0 did.

 

Thanks.
Euh what does it mean "AFAIK"?

Thanks to your lights I will try to change some value in CPU PLL M/N Control and Frequency Select Source.

 

Yes it's exactly what I was preparing to do. I will try just if there is a resistor around.
And after, make a switch with FS_B, Vcc, Vss (or GND).
First I have to find a soldering iron, multimeter, jumpers, pins...

 

Ok, I finished the changes on the clock generator.
I installed a switch which change the FS_b value. 1 for 200Mhz and 2 for 266Mhz.
It seems to work because when select 200Mhz, the computer works exactly as before. When I select 266Mhz, it boots, starts XP but I have even no time to open my session, and the computer reboot again...

I think about 3 possibilities:
-The CPU heat too much
-The GL960 chipset heat too much
-Or the memory configuration is not appropriate.

For memory, I tried to extend each clock latency time proportionaly by using Thaiphoon's editor.
I clicked "Next" and "Reprogram SPD EEPROM". I checked the report, all seems ok.
But, when I checked whith Sandra or CPU-ID, no changes.
And when I reboot and launch Thaiphoon again, no changes... The memory is like before. Is Thaiphoon not able to write my memory???

 

I think your problem is RAM. Moral Hazard discovered some RAM appears to not allow spd_table entry to be modified by Thaiphoon or spdtool. Your 200->266Mhz overclock means your DDR2-667 RAM is now running at 887Mhz (using 333Mhz table entry). This is probably the reason you are seeing a BSOD/reboot. Do you have access to other RAM to test with? Even 1GB just for testing purpose??

 

yes, that's right.

@saebasan, can you try it with spdtool?

Also can you tell me the brand of your ram.

BTW, AFAIK means:
"as far as I know".

 

So actually, I have 2 memory hynix, 1 & 2Gb.

I tried Thaiphoon on the 1Gb of the modules. It seems I can't really change latency.
But what should I change exactly, just the first 5 value (CL, tRCD, tRP, tRAS, tRC) or all (tRFC, tRRD, tWT, tWTR, tRTP too~~~ ) ???

I tried whit a 1Gb DDRII-667 Kingston, but I not able to make the OC work, so I changed memories...
After that I tried Thaiphoon on a Transcend 2Gb DDR2-800, ASint 512Mb DDR2-800 too. I growed up all the value to look like the 400Mhz equivalent values (and a little bit more because in fact memories should work at 447Mhz, right?)
First, it seems Thaiphoon don't really write what we configurate.
Second, it killed theses two last memories which don't work anymore now, neither in my laptop, nor in my Asus Eee.

Spdtool is it really better?

 

yes spdtool is better, if it has a problem it will actually tell you what it is.
This will be usefull to see if the SPD on the stick of ram allows modification.


Also you can fix the other ram, you will have to "hot flash" it.
Try to use a good stick of ram and a broken one together to see if you can boot like that, then reflash the bad stick to fix it.

 

Here some pics of the modif. The goal is to connect FS_b either on Vdd or Vss (1 or 0), by a switch.

Before


After



Green = FS_b
Red = Vdd
Black = Vss
And the switch is on the other side of the mother board.

 

What should I change exactly?
As for you, what did you changed in pratice on your memories ?

 

how are you disconnecting FS_b from Vdd?
Or does it not need to be done?

 

In spdtool I changed "Cas latencies supported".
If it supports "4,5,6" change it to just "6" (highest supported value).

 

FS_b leads to a resistor, he can apply apply GND straight onto the FS_b pin without lifting it, so there will be different logic levels on either side of the resistor:

Code:

200Mhz: BSEL[2]=FS_b=1
266Mhz: BSEL[2]=1, FS_B=0 (BSEL[2]=1 ensures no multipler lock-out)

200Mhz:
BSEL2 -------- [ resistor ] ---- FS_b
(1-VCC 3.3V)                    

266Mhz:
BSEL2 -------- [ resistor ] ---- FS_b
(1-VCC 3.3V)                    (0-GND)

 

ok, I understand. thanks

 

Ah Ok. It's just needed to change CAS latency, not all the values...
So I will try to use spdtool because in Thaiphoon if one value is allready set to CAS latency 6, it don't let me put another value to 6 too.
Thaiphoon, always try to make by example for a 400,333,266Mhz frequencies able memory, -> 6,5,4 CAS latencies or 5,4,3, and so on. Impossible to make 6,6,4 or 5,5,3

 

FSB 800Mhz downclocking with T9900 based on FSB 1066?
I really don't understand people who doing this ?!?!?!?
Why would you downclocking ????
So go and buy CPU with lower FSB and frequency
Why You bought High CPU and now you want cut the speed ???
nonsense,nonsense

 

OP's GL960 chipset only supports 800Mhz FSB officially. So it's an enquiry if the 1066Mhz series-4 penryn CPU would be downclocked with the slower FSB.

 

Yes Nando, you understood exactly. Some peoples succeded to install T9100 & 9300 on my acer.
So I wanted to know, if it is possible to 'connect' 1066Mhz FSB CPU even downclocked to 800, in order to put up later the GL960 from 200 to 266Mhz (so 1066Mhz FSB), AND finally make theses processors work again at their 'normal' core speed... (by example a T9900)

@Evoss-X: Here is the place for someone who wants to break the wall of 'impossibilities', and not just criticizes for nothing.
But anyway Evoss-X, no one asked you to understand anything.
You can sleep away, far away, deeply in your certainties.

 

Have a read of the bottom of this post. The safe answer would suggest "no", go a T9300/T9500 and be done with it. The "breaking impossibilities" answer would suggest "maybe", likely requireing a bios with series4 cpu microcode flashed on it. I would like the latter to be proven