Future Undervolting | NotebookReview

Here is something that might affect future undervolting
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Microsoft said:

The XPSS (Extended Performance States)

This optional ACPI object is nearly identical in form and function to the _PSS object defined in the ACPI 2.0 specification. However, the XPSS allows the platform to provide 64 bits of data for the Control and Status values for each individual performance state defined, whereas the _PSS object only allows 32 bits of data. In addition, the XPSS allows for a 64‑bit mask to specify which control bits in the Performance Control Register should be updated, and which status bits should be compared after the control value is written. If the XPSS is present, the generic processor driver in Windows Vista and Windows Server 2008 will use this interface instead of the interface described by _PSS.
Name (XPSS, Package()<o> ></o> >
{ <o> ></o> >
// Field Name Field Type<o> ></o> >
Package () // Performance State 0 Definition P0<o> ></o> >
{<o> ></o> >
CoreFreq, // DWordConst<o> ></o> >
Power, // DWordConst<o> ></o> >
TransitionLatency, // DWordConst<o> ></o> >
BusMasterLatency, // DWordConst<o> ></o> >
Control, // Buffer<o> ></o> >
Status, // Buffer<o> ></o> >
ControlMask, // Buffer<o> ></o> >
StatusMask // Buffer<o> ></o> >
},<o> ></o> >
<o> ></o> >
<o> ></o> >
Package () // Performance State n Definition Pn<o> ></o> >
{<o> ></o> >
CoreFreq, // DWordConst<o> ></o> >
Power, // DWordConst<o> ></o> >
TransitionLatency, // DWordConst<o> ></o> >
BusMasterLatency, // DWordConst<o> ></o> >
Control, // Buffer<o> ></o> >
Status, // Buffer<o> ></o> >
ControlMask, // Buffer<o> ></o> >
StatusMask // Buffer<o> ></o> >
<o> > </o> >
}<o> ></o> >
<o> ></o> >
}) // End of XPSS object<o> ></o> >

Each performance state entry contains six data fields as follows:
· CoreFreq. Indicates the core CPU operating frequency (in MHz). <o> ></o> >
· Power. Indicates the typical power dissipation (in milliWatts). <o> ></o> >
· TransitionLatency. Indicates the worst-case latency in microseconds that the CPU is unavailable during a transition from any performance state to this performance state. <o> ></o> >
· BusMasterLatency. Indicates the worst-case latency in microseconds that Bus Masters are prevented from accessing memory during a transition from any performance state to this performance state. <o> ></o> >
· Control. Indicates the 64‑bit value to be written to the MSR-based Performance Control Register (PERF_CTRL) in order to initiate a transition to the performance state. <o> ></o> >
· Status. Indicates the 64‑bit value that OSPM will compare to a value read from the MSR-based Performance Status Register (PERF_STATUS) to ensure that the transition to the performance state was successful. OSPM may always place the CPU in the lowest power state, but additional states are only available when indicated by the _PPC method. <o> ></o> >
· ControlMask. Indicates the 64‑bit binary mask that will be applied to the value read from the MSR-based Performance Control Register (PERF_CTRL) in the Read/Modify/Write scenario to transition to a performance state. <o> ></o> >

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Future Undervolting?

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