Process nodes, half-nodes and what they mean (X nm)

I know that miniaturization of microprocessors is generally measured in terms of process nodes, such as 90nm, 65nm, 45nm, 32nm, 22nm, 16nm and so on. At the moment, the most advanced process utilized in mass production is 32nm.

OK, so with this in mind I would like to ask: What exactly is it that the nanometer measurements measure? I know it is some sort of feature size, but what feature are we talking about?

I tried to read up on it a little bit and it seems that a frequently cited measurement in miniaturization is gate length, but this does not actually correspond to the nanometer number that represents each node, so something else must be the determinant of node nomenclature.

Also, I would like to enquire about half-nodes, such as 55nm, 40nm, 28nm, 20nm and so on. I had assumed in the past that these are the same as nodes, except at non-standard (half) numbers, but lately I have read some processes being referred to as 45/40nm process, 32/28nm process, 22/20nm process and so on, which left me wondering if they actually have different feature sizes, or if it is just a case of different nomenclature for the same thing.

Anyway, I hope this is the correct forum for this type of question.

 

All kinds of features -- transistors of various sorts and the lines between them. The definition in the wiki is for DRAM: it's half the distance between adjacent memory cells. Of course, neither CPUs nor GPUs are made purely of memory cells so this is more or less an average feature size. The definition is vague because the concept is vague -- not everything on a 32nm CPU is at the scale of 32nm.

This one is easier: they actually have different feature sizes. A "node" is a reduction of the feature area (and hence an increase in the number of transistors one can fit on a chip) by a factor of 2. For example, in going from 45nm to 32nm, the area decreases from 45*45 = 2025 to 32*32 = 1024 which is roughly a factor of 2. Once Ivy Bridge is released, we will have 22nm CPUs which means another factor of 2 (22*22 = 484 which is roughly half of 1024). A half node means the area only goes down by about a square root of 2 (as you've probably noticed, these are only approximate -- since it's a vague term to begin with, they pick the closest whole number for marketing purposes).

Giving two distinct processes (e.g. 45/40nm) can mean a couple of things. First, it could be that some of the parts were manufactured with one process and some with another with the name of the product not changing to account for the difference. No CPU maker has ever done this, but GPU makers have. Second, it could mean that some of the chip is of one process while the rest is of another. Arrandale is like this: the CPU is 32nm while the GPU is 45nm. Finally, it could mean that whoever is writing the article doesn't know exactly which process is used -- it's either one or the other.

 

Great explanation. Thanks

 

OK, so half the distance between adjacent memory cells - that does actually explain it. I do understand that various features can have different sizes, hence my question which feature is actually measured by the number of the node.

Follow-up question: As you have pointed out, the node represents the distance between memory cells and various other features at a given process node have different sizes. Given this, are the sizes of the other features standardized at the same process node, or can they differ among various manufacturers. For example, if the gate length at Intel's 32nm process node is 25nm (not a real example - I just made it up for illustrative purposes), does that mean that gate length at Global Foundries 32nm process node will also be 25nm (i.e. feature sizes are standardized at a given process node), or can the size of the same feature differ on the same process node depending on the company's specific process even though the distance between DRAM cells is the same?

I have indeed noticed that a two node step equals halving of feature dimensions (meaning that a single step halves the area) and half-nodes did appear to be half a step, but I became unsure of it after seeing articles mention the 45/40nm, 32/28nm, 22/20nm and so on, so thanks for clearing it up and confirming how it actually works.

 

It can vary both between manufacturers and within a single manufacturer's product. It's standard for DRAM because DRAM cells are a rectangular array. CPUs and GPUs are not like that -- there are many structures on a single chip and some of them need to be smaller while others can be larger. The number of nm is a characteristic scale, not an exact description of individual circuits.

 

Every process will have a set of rules.

Two different FABs might both be 40nm but they will have a different rule book. Only by reading these rule books and then designing a chip could you really appreciate the finer differences.

So really all people need to know is that with a smaller process you can fit more on a chip and it should use less power.

 

Thanks for the great explanations. It is interesting to hear that different manufacturers may have different sizes for the same feature at the same node. Although I somewhat suspected this may be the case, I wasn't sure.

I suppose it also means that theoretically-speaking if the best features of say Intel's and Global Foundries' 32nm processes were combined (using the smaller features from each) the resulting combined process would yield a smaller average feature size than 32nm. Sure, this is purely theoretical, but still interesting to speculate on.

 

There are different methods and tweaks for each step of the process. While I am sure direct collaberation would be impressive, it would not be an immediate improvement.

Did you know FABs have some of the deepest foundations in the world and that trafic outside can reduce yields because of the vibrations of cars?

A single machine can cost hundreds of millions of dollars.

 

OK, that does make sense.

That's fascinating! I assume it poses a dilemna for fab location - one wants it to be close to lines of communication, but if yields are affected by traffic, being too close to a highway or an airport would be counterproductive.

 

Did you also know that wafers are sliced from an individual seed crysal, spun in the moltern mixture of silicon doped with the right mix of chemicals? It is then drawn up so that the end cylinder is a single massive crystal.

Fab1 in Germany has had $6 billion dollars invested into it so far and employs over 2000 people.

 

Ouch, $6 billion is certainly not pocket change even for large corporations. I guess that's one of the reasons why companies are moving to larger wafers to increase yields and counteract the increasing capital costs of the equipment.

 

Thats why AMD spun off global foundries. Keeping up with intel was impossible.

However by supplying more companies you get more demand, you can pump out more chips.

AFAIK intel spends the GDP of a small country on its fabs.

 

True, but AMD could have simply offered the use of its fabs to other companies without spinning them off. I suppose it would have been harder to sell, though, as potential corporate customers might be worried that AMD might be 'inspired' by some of the trade secrets in their products.

 

Also their agreement with intel would have stopped that.