Ryzen vs i7 (Mainstream); Threadripper vs i9 (HEDT); X299 vs X399/TRX40; Xeon vs Epyc

At this point, between the new HPET hits with Spectre and meltdown patches, shoddy software programming (looking at OS and software for the OS here), etc., which have caused many ups and downs in performance (it is being seen with both CPU mfrs., so I am leaving them out on this comment, not that they do not need called out on occasion), it is just a pain.

What I have been looking at since last being on here was getting Win 7 installed on an NVMe drive for this PC again. Talk about headaches. But, I find it interesting that the people on HWBot are blaming AMD for the RTC issue in Windows 10. If they thought about it for two seconds, they would understand why that makes little since. Clock gens are usually on the MB or Chipset. They only Zen based CPU with chipset on board is the Epyc CPU. Windows 7 does NOT have the RTC problem, which means the problem is not hardware based as a properly coded OS, Win 7, reads the RTC just fine. Instead, it is Windows 10 that is the problem with RTC. In fact, every CPU before Skylake had an RTC problem. Now, there is a chance certain hardware mitigations could help with this issue, but I'm left still wondering why M$ didn't fix the problem, which has been found on Win 8 for some CPUs, then on Win 10. But, that is the problem, if you blame the smaller company in all this, you can absolve blame without solving the issue.

Please, someone correct me if I'm thinking off base here, considering RTC I was under the impression came from the MB here.

 

Do not get me wrong, I think the RTC has something to do with it. It does seem there is a secondary setting that is by default enabled by the RTC being set in W10 that does not by default get unset by disabling HPET, This setting either does not get enabled at all in W7 or properly switches on and off. The fact the RTC performance issue seems non-existant in W7 seems the secondary setting is not effected. Shame on you M$ as it seems wince W7 the implementation of HPEC is broken!

 

maybe ms and intel working together on this to rid of amd who knows.

also check out:
https://wccftech.com/intel-flagship-coffee-lake-s-8-core-es-cpu-gets-cinebench-benchmark-leaked/

i donno looks like bull crap, might be a genuine 8 core ES CPU but the frequency must be overclocked. at 3.1ghz 8 core beating a 10 core cpu at higher frequency is nonsense.

also if you look at the table, it shows z370 is gonna work with 8 cores but is that confirmed? or just wccftech being wccftec

 

ill be looking forward to @Prema making that 8 core cpu compatible with Z170 boards

edit: well would u look at that @ajc9988

Link: https://wccftech.com/amd-ryzen-thre...-thread-cpu-specs-performance-overclock-leak/

IF (i know i know its wccftech) that holds true, well be looking at 3.4 ghz base and 4.0 ghz boost with 4.2 ghz single core boost on the 2990X.... HOT DAYUM!

 

So, the z370 compatibility was confirmed, posted by papusan awhile ago (like a week or two ago).

An 8 core beating last year's 10-core, but being on the 14nm++ and likely clocked and overclocked much higher than the 10-core, it may be possible, but grain of salt.

I don't know about it, but if the 32 can hit that high, then it isn't a contest. But, I noticed a couple things that make it suspect. 1) these chips supposedly have revision B. Those are Epyc dies, note Ryzen dies. Now, there may be tweaks in play on Epyc dies vs Ryzen that reduce their heat and power reqs, but, I am weary. I'll wait for something more concrete, but if true, as Garth would say, shawing!!!!

 

imo it has to be overclocked, 7700k does about 1100 at 5ghz and this doubles it at 2200. 8 core 5ghz, no way to explain it.

 

That 8 core CFL has to be overclocked. Has the Z370 compatibility been confirmed? I don't trust anything until Intel gives us their blessing. I fully expect to buy a new board.

Also the Ryzen image appears to be faked.

https://twitter.com/johncmiller96/status/1009192176864120841

 

2200 on 8 cores shouldnt be too hard to achieve considering the 2700x has already been demonstrated to be able and break 2000 on CB15 with fast RAM

but yes, definitely overclocked. im getting 1125 CB15 with my 7700k at 5.1 Ghz, so a score of 2212 with double cores should also be around 5-5.2 ghz, depending on OS optimization.

Sent from my Xiaomi Mi Max 2 (Oxygen) using Tapatalk

 

The 6104 for a 3.4 base and 4.2 single core sounds about right to me. The other overclocks of the system seem a bit slow, I was expecting a full overclock at 4.1 to get around 7000 in CB R15. This could be due to the fact only 2 of the four CCX's have direct memory access and the other two have to go through the IF. All I can say is stock if it does these clocks it is a must have here and I probably will not overclock at all either.

https://wccftech.com/amd-ryzen-thre...-thread-cpu-specs-performance-overclock-leak/

And this was one of the round AIO's too, not a true TR plate!

Edit; OMG look at the vote on the bottome right now, interest AMD 32 core 3.548 and Intel 198 Votes.

 

haha the results of that vote dont surprise me, its an article about TR, after all, so people more interested in AMD HEDT are more likely to read that article anyways

 

Usually they are not that one sided. Especially since the intel 8 core article is linked to this one as well for the reference.

 

The Intel Fiasco purge has begun... the heads are rolling at Intel, starting from the top...

Brian Krzanich out as CEO of Intel
Bob Swan is in the new hot seat
Jun 21, 2018 by Charlie Demerjian
https://semiaccurate.com/2018/06/21/brian-krzanich-out-as-ceo-of-intel/

"It looks like Intel’s CEO Brian Krzanich is out, replaced by Bob Swan. SemiAccurate thinks there is a lot more to this story than a past consensual relationship though.

In a terse release today, Intel said exactly what SemiAccurate just said, just in a lot longer form. Officially BK violated Intel’s non-fraternization policy, something which SemiAccurate strongly doubts lead to this ousting but it sure makes a good cover story. That said, technically it is a firing offense, but given the conduct of past people in the same seat and the consensual nature claimed, it should have revived a low end of the scale punishment.

Why do we claim this is a cover? Intel’s 10nm process flat out doesn’t work. The company is about to lose huge chunks of their core server market to AMD and has no way out. Their current efforts to hold the line and prop up margins have seriously alienated customers and there is no end in sight for the slide. To make matters worse, their roadmaps are a complete mess and change faster than the ink can dry. Some have even suggested that Mr Krzanich knew the train was about to run off the rails, we sure did.

When times are tough and faith is about the only thing holding your stock at it’s current highs, the last thing you want to do is fire your CEO for cause. Intel has some very smart people on their board and in upper management, they know this. That said they needed to do something and, well, a slap on the wrist offense becomes an interim CEO. There is much more to this than a simple consensual affair, when the depths of Intel’s woes become clear, so will the reasons behind this transition."


As the cleaning up at Intel continues, say bye bye to any outside the box non-CPU related expenses, like GPU projects.

I hope this gets Intel on track to put their time and effort into the new architecture CPU development, so Intel can get the Meltdown / Spectre and related architectural vulnerabilities behind them.

As faith in Intel wanes, that should open the field further for AMD to push into any market they can fit their Zen architecture, and allow the AMD server market to flourish.

Even if consumers are suckered into the 8 core CPU release of Intel's dead-end architecture, the datacenter financiers have to realize that the current Intel architecture is no longer a good investment.

Between now and a couple of quarters after the release of the new Intel CPU architecture, AMD should be able to take advantage with their superior price / performance Epyc solutions.

 

One could say, he went out with a bang.

 

So goes the cover story

It would be a mistake to accept the cover story, as Semiaccurate illustrates in their article.

Intel will continue to make believe it's business as normal, until the tip of their tallest mast disappears beneath the waves.

 

just saw this picture havent read the article but, assuming this is intel cpu pre-patch:



damn amd catching up to intel. as per the core AMD is a newer architecture with ryzen so kinda expected with lower latency, just issue with IF and once thats fixed, AMD will most likely have higher overall IPC by easily 5-10%.

all thats really holding AMD back is the ccx & foundry issue. once infinity fabric is fixed and on higher core count its almost no brainer to go AMD cause frequency can only go so high due to heat for both intel/AMD.

 

Still a big latency difference between cross-CCX and ring bus or even mesh. They should add the numbers from the 2200G/2400G which has no cross-CCX latency (single CCX).

 

yea that would be good idea, this might work well with most ultra book or notebook, great performance for half the cost of intel's cpu.

also i jsut read their test bed, doesn't include intels patching so those latency are intel's best case scenario pretty much. even semi-patched ryzen is already beating intel on the core/lowest level. intel wont have anything new from ground up for at least another couple of years, ryzen is most likely the way to go from now to 2021. if they further get better on foundry side then they'll be unstoppable with that power consumption.

easy 4.5 to 4.6ghz O/C while using only 3/4 of intel's power at same frequency is pretty impressive (rough guess). lower temp = higher room for OC. lower frequency is fine as long as IPC is 5-10% better would make up for it.

 

The calc we came up with is 5.2GHz. Also, we calculated the TR2 numbers for 6300, it is around 3.57GHz with fast ram to achieve it on the 32 core chip.

 

Do I need to school you on mesh latency? It is literally only around 10-15% faster than IF (gen 1 Ryzen; it is all based on ram speed, which the timing calculator and compatibility updates have gotten so that 3200MHz ram is what brings it down drastically).

Edit: let me see if I can run the latency with the free version of sisoft

 

Foundry side is done. GF is targeting 5GHz HPC/server chips and already said they are achieving that on their runs, meaning AMD will fulfill that to the server market. They used their clout to change GF fin pitch to match TSMC so that they can freely switch between the fabs when needed without a full redesign and tapeout. They are going to win hard next year because Zen 2 is designed to compete with Ice Lake. Ice Lake is pushed for next year as even Intel won't give a quarter for volume production on 10nm, and Ice is 10nm+ process. Intel really needs EUV BAD to address yields which are due to defects of quad patterning and the single dummy gate. RichieC and I were talking about this last night on discord.

Meanwhile, MB manufacturers laughed at Intel saying the new HEDT platform in Q4 and said it will be pushed into 2019. That means a delay in Cascade-X/SP hitting the market, which gives even more time for AMD dominance on the HEDT platform, and BK even said all they can do is try to limit AMD growth to under 20% (he said 14-20%) in the server market for market share. Considering they were so low before Ryzen, literally like 0.1% server market share, they are about to be flush with cash. That buys R&D, which GF is talking skipping 5nm and going to 3nm, so after 7nm+, Zen 5 (they are skipping number 4 for superstition) should be another decent jump in performance.

So, AMD will have frequency and IPC improvements coming and Intel has nothing. Around 2020 is the earliest they might have something competitive, with around 2021 bringing the iCore replacement uarch, which means we will then likely see a multi-die solution by then.

 

The problem is Intel dipped into the "what we have not released yet" well. While doing this they took a major price hit in all CPU markets. All this while not establishing a major dominance in performance. There was a time this would have worked but no longer.

Not too long ago casual tasks and your desktop were severely effected by your CPU performance. I am talking even as recent as the Core 2 Duo days for Intel. At that time AMD had nothing to even compare to those. With the advent of Icore and SSD's the casual desktop and general workstation performance became less dependent on an upgraded CPU, to a further extent with each generation.

Now it is at the point giving up 10% or less of the IPC make a lot less difference. In this manner the new Ryzen becomes more competitive other than the expensive super high frame rate gaming systems. Now with the advent of TR2 and Epyc 7nm Intel seems to be looking at an old tactic, as the say what is old is new again, VAPORWARE!

 

I am highly suspect of this with TR2. I think this new CPU is memory bandwidth limited. Similar to taking a present TR and running just dual channel memory. This may be even why they never released a 32 core originally too. Now Epyc 7nm does not have the issue as there are 8 memory channels.

Evidence of this is with the all 32 core overclocks the CB R15 score does not seem to scale well. It could too be the IF, as in double the data traffic over TR1. In either case faster memory may help alleviate the bottleneck. As I have said before, bring on the silicon, I wan'a play too!

 

Sure. I will bookmark this one. Thanks

 

https://www.overclock3d.net/news/cpu_mainboard/globalfoundries_expects_great_things_from_7nm_-_clocks_in_the_5ghz_range/1

"Q17: Does the first generation of 7LP target higher frequency clocks than 14LPP?

GP: Definitely. It is a big performance boost - we quoted around 40%. I don't know how that exactly will translate into frequency, but I would guess that it should be able to get up in the 5GHz range, I would expect"

 

I’m on my own. Can’t share. Wrong or not

 

Hey, I'm just trying to show you that your ardent stance will come back to bite you on the Intel/AMD offerings next year. Writing is already on the wall.

 

I’m sure you will get more info

 

If you do an extrapolation, if IPC remains the same, but you reach 4.6 on 32 core AMD TR3 on all cores, (Server gets 48 next year and potentially 64 that year or the year after) you are looking at 8121 in CB; at 5GHz, you get 8827. Considering what Intel hit with extreme cooling, if AMD delivers on even single core boost 5GHz and 4.6GHz all core, they smash Intel considering this chip goes against Intel's cascade, which is around 6000 near stock and 7300 for 5GHz on extreme chiller. In fact, AMD would only need to get around 4.15 on all 32 cores to match 7300 with their current tech. So, with the GF official saying that he guesses it should be able to get up to the 5GHz range, it will just crush Intel's offerings, plus will finally be more competitive on single thread. Really, considering Intel will not give a quarter for 10nm production, you are looking at Q3 or Q4, and there is no guarantee that means anything because that sounded like applying to cannon, not ice, lake. That is some serious ownage!

Edit: in fact, if the new 32 core runs at 3.4 all core boost, and you add 35% to frequency, you come to 4.59 (basically 4.6). If you do 40%, it is 4.76GHz. Just to show where the math leads.

 

Guesses and “if”. I’m on my phone

 

My methodology was to divide a score achieved with good memory and tight timings (my own, actually), by number of threads, then by the frequency used to get a standard per thread performance in multi-threaded tasks. I then multiplied it by the number of threads for the 32 core chip, then would multiply by the frequency to arrive at the approximate scores. When targeting a specific score to find the frequency, then it was the score divided by the standardized performance per thread times the number of threads. So, stock or with slower memory with looser timings, you would get a reduction in score, but just trying to give an idea on where it is headed.

 

‘This ain’t worth much.

Same as some stated below 1400 for 8700k

 

@ajc9988 in that picture graph i quoted from tomshardware. i briefly read it on toms but they didnt really mention it. why is TR has that extra measurement of latency "die to die"? if 1700x and 2700x didn't have them then TR1 shouldnt have it either.

that green bar die to die latency is pretty huge which drops overall performance of TR1, i'd expect TR2 to be yet another well improved going by the trend 10-15% over TR1 is quite something but not enough.

isnt TR the same as 1700x/2700x just with more CCX, whats this die to die thing.

 

The TR2 is still quad channel memory. Only 2 of the CCX's are direct to memory from the IF the other two go through the IF to get to memory. So yes, over Intel there is going to be higher latencies. In the end though the overall wider pipe and high speed memory make up for a lot.

TR2 though will have an issue over TR1. This as I was saying when al cores are flooded essentially two times the data is flowing back and forth too RAM and worse the IF has to juggle all that work so it is well over double the originals workload. This well could be causing issues above the full core 3.4 GHz boost.

If the IF and memory can handle the workload without bottlenecks then an all core 4.12 GHz should yield CB R15 of over 7,200. As it looks from the leak we only got 6400 while the stock 3.4 GHz, single core 4.2, got 6,100 where that amount does not seem bottlenecked.

Would I like 4.2 GHz without a bottle neck. I surely would! Will I be happy stock at 6,100 in CB R15, well since it blows every thing else away, guess?

 

TR has two 8 core dies, with each die having two CCX complexes. Now, last night, I did run it on my machine, and although it reads higher than the ping between cores that PCPer did, it breaks it down further than they did. Now, I ran it twice, and received an average for die to die that was around 220ns, but noticed a note at the bottom of the notes section in sisoft sandra. It required changing the lock memory settings in the security settings to have larger mem blocks accessible. After I did that, the breakdown was around 12ns, 40ns, 120ns, and 180ns. I will run it again in a little bit and post the exact averages.

The beauty of AMDs design is that they have created a scalable arch. This means they can keep slapping more 8-core dies onto a PCB, so long as they can do the traces between the multiple dies to connect them together with IF. So, the die-to-die communications would be comparable, but slightly faster than, Intel's socket to socket if you have a 2 processor board. Now, with the 24 and 32 core chips, those will have 4 dies, not two, but with the I/O and memory channels severed on two chips. This is what TANWare was discussing about latency on the two new dies added.

I call ******** on the speeds. They had those scores on there saved while running it on an Intel 8-core, IIRC. That looks more like single core boost because that chip, with 8-dies, CANNOT hit that without extreme cooling.

As to your fears, they are unfounded. EPYC works. They trace mirroring core to core connecting CCX to CCX. So, for the two new dies, each time it has a memory call, it must first hop to the mirroring core with the memory controller on the CCX, then out to mem, then roud trip it. That slows it down, but shouldn't be a 15% on top of the 10% inefficiency on scaling already seen on multi-die, even without the direct mem access. Already we don't see that sort of lag when it has to go die to die to get it from the other memory channels. That is why, along with the heat of four chips, that I call BULL! The CPU-Z on a different article showed 3.4GHz on the 2990X, meaning those, at best, are reading the single core or XFR scaling on a single core, not the all core speed.

 

1700x/2700x is just one 8 core die. TR is two 8 core dies plus two dummy dies. TR2 is four actual live dies. so die-to-die latency only plays a role in configs with more than one single die on the package, naturally

Sent from my Xiaomi Mi Max 2 (Oxygen) using Tapatalk

 

Actually, we do not know if the 8 and 16 core variants will have all four dies live or not. We know for sure the 24 and 32 will, with the 24 core having one core per CCX disabled, likely mirrored.

 

man thats rather disappointing. its great to have so many cores at such a low pricing and i know its still faster than intel's duo/quad socket CPU via QPI but the high latency really turns it down a notch. really want to see a flawless AMD CPU maybe we'll have to wait till 2019 or 2020 for their retake.

intel on the other hand mesh is also a huge problem, as long as they dont allow mesh overclocking past a decent frequency imo its just as bad, and i dont even want to think just how much heat it'll produce overclocking it.

 

My understanding. With each CCX there is a dual channel controller for direct memory access. Each CCX controls a division of it's memory, Ryzen is direct access so no IF access needed to other CCX's for the memory map. With TR there are two CCX's with direct access and each splits the memory map in 1/2, so for a core to access memory controlled by another CCX it must do so though IF. With TR2 now there are two cores with no direct memory map access so IF has to be used 100% of the time. With Epyc all four CCX's have a direct memory map for its 1/4 of the memory. Again for a core to access memory another CCX controls traffic is through the IF.

This is not a defect of IF but actually the intended design. While intent is to reduce latencies as much as possible this is a sacrifice of the modular design. As you are now starting to see the advantages of the scalable design it has its limitations as well.

Now as memory speeds increase along with further generational tweaks to IF this should work out fairly well . The biggest problem for Intel is the design seems to have hard limits and no further scalability. With their 28 core they seem to have one last shot, but without a further innovation they then may be left behind.

 

Intel will be joining the multi-die party most likely as well. Just run the numbers on how many smaller dies you can get out of a wafer with a defect density versus a monolithic die. With that said, what I hope will happen is that AMD does a single controller chip, puts all L3, I/O, and IMCs on it, and then does something to divorce the gear rating of ram and IF, with having an independent, overclockable control of the IF on the control chip, which can allow for gearing it better as needed. Also, with a separate control chip, you could bin the IMCs better, allowing for more control over trying to increase the memory clockspeeds. Now, all chips would be hit with the IF latency to go to the control chip to access L3, and it would be similar to the die-to-die latency (so more work would need done on fixing the latency, which is why having the clock speed of IF on that chip could help), but it does solve some other problems or complaints.

https://fuse.wikichip.org/news/1064/isscc-2018-amds-zeppelin-multi-chip-routing-and-packaging/
Good article on their chips and how the mem arch works. I'm reading through it right now (or until I go to cook dinner). It is really detailed.

https://wccftech.com/amd-zeppelin-soc-isscc-detailed-7nm-epyc-64-cores-rumor/
If you want to just skim before reading the detailed one.

 

well according to latest news we cant even be sure that AMD will release any TR2 other than the 32 core sku.

so 2990x definitely, 2970x maybe, 2950x unlikely(?) and i had no idea they were even planning to release an 8 core TR2?!

Sent from my Xiaomi Mi Max 2 (Oxygen) using Tapatalk

 

ThreadRipper 2990x + "Wraith Ripper" info starts at 01:05, ends at 02:50:

Intel CEO FIRED over scandal??
Published on Jun 22, 2018

Spoiler: NEWS SOURCES

TSMC Invests $25B in 5nm
https://www.cultofmac.com/556985/appl...
http://www.hexus.net/business/news/co...
https://www.itproportal.com/news/taiw...

Threadripper 2990X Leak
https://www.hkepc.com/16912/
http://www.hexus.net/tech/news/cpu/119426-32c64t-amd-ryzen-threadripper-cinebench-scores-surface/
Wraith Ripper
https://www.anandtech.com/show/12996/amd-teams-up-with-cooler-master-for-wraith-ripper-megacooler

8TB NVMe SSD from Samsung
https://www.techspot.com/news/75187-s... .
https://www.anandtech.com/show/13003/...
https://news.samsung.com/global/samsu...
https://www.zdnet.com/article/samsung...

QUICK BITS:
Knuckles VR
https://www.cnet.com/news/valves-new-...

XBOX VR Dying
http://www.hexus.net/gaming/news/xbox...
http://www.hexus.net/gaming/news/xbox...

Intel CEO Resigns
https://linustechtips.com/main/topic/...

Facebook Group Subscriptions
https://www.kitguru.net/channel/gener...

China Lifting Firewall to promote tourism
https://www.theverge.com/2018/6/22/17...

Titan V CEO Edition
https://www.kitguru.net/components/gr...

 

I have to say skipping the 24 core and below on the TR2 is not a bad idea. The issue I can see will be with these other variants that using over 1/2 the cores places the load on CCX's that do not have direct memory access. In theory a 16 core TR2 could perform worse than a TR1 over 8 core loads, unless the 12nm can give it that much of a performance advantage. Even a 24 core could be hit unless the load is above 16 cores or below 13 cores. Once at 7nm this may not be an issue.

Now this is all speculation of course.

 

well it does make sense, currently ryzen 2000 series has decent improvement over 1000 series if you use a fast enough memory that 2000 series can use and 1000 cant. until 7nm AMD might not restructure their cpu so gotta wait until at least 2019 to see what zen 2 is capable of.

 

The only thing we have to go on, besides AMD publicly mentioning the 32c ThreadRipper Gen 2.0, is AMD's Jim Anderson interview where he says AMD will continue to offer the ThreadRipper Gen 1.0, assuming all will persist 8c / 12c / 16c.

So the only question is will ThreadRipper Gen 2.0 offer 24 core count CPU?, and will the ThreadRipper Gen 1.0 CPU's cover the lower core counts with no other TR2 than the 32c?

AMD's Jim Anderson discusses 32-core Threadripper 2
PCWorldVideos
Published on Jun 6, 2018
AMD's Senior Vice President Jim Anderson discusses the new 32-core Threadripper 2 with Gordon Mah Ung. Threadripper 2 will be modeled on the second-generation Ryzen processor, based on 12nm, and the Zen+ architecture. It will use the same TR4 socket allowing customers to shift from one Threadripper generation to the next.


Unless you have a quote from after the 32c TR2 reveal that suggests there will / won't be a 24c TR gen 2?

GN is claiming a 24 core Threadripper being released <= Click
https://www.reddit.com/r/AMD_Stock/comments/8ou8y3/gn_is_claiming_a_24_core_threadripper_being/

 

I think the quote is they for a time will co-exist. As far as not 24 count, that is all SPECULATIVE! That GN video was even before the 32 core was announced.

 

Now, they changed the production lines for double the active cores. And doing market segmentation, that is fine. I don't care what they call it. But, here is my thoughts on what not at least refreshing the 8-16 cores tells someone like me:

They did refinements to improve latency related to IF, improvements to cache and IMC, etc. If not brought to the 2-die chips, there may be other reasons, but I see two that may stand out: 1) they do not think current owners would upgrade because gains at 12nm are so little, in part basing on the upgrade data they had on the 2000 series, or 2) these improvements are mitigated once scaled to multiple dies, so they do not want that to be seen or analyzed, which could result in bad press. I think the latter makes more sense there as it may effect sales to people not on the platform. But, there is no word on an X499 chipset refresh, the TR2 will use X399, and any performance effects of the extra dies not having their own IMC or IO will be limited critiques because it is related to the new product lines rather than the lower. Now, doing 8-16 on anything but two dies doesn't make sense, I think we can all agree with that, but if not doing at least a refresh rather than TR2, or giving a new revision or whatever, I want to know why as it is one of those things where unless a person needed the 24 or 32 core, they have to wait another year to get a new product. With that said, most people do not upgrade yearly, so making them wait two years to get that sweet 7nm and not wasting R&D on an incremental step like Intel does each year makes sense, especially if the gains are modest, which would allow more focus on graphics and 7nm designs. If that is the case, they should just say it. Nothing wrong with that, to be honest. But, speculating the fixes/tweaks do not scale well with MCM could hurt. Saying it doesn't meet a new standard trying to get a larger jump in performance between generations, OK. And some Intel people (fanbois) would run with the headline that the tweaks don't scale well, which would hurt them. But, if that is the case, then I kinda like the thought of having Zen 2 TR3 ready for computex, which is the halfway point between their August cadence and what TANWare called for, releasing in April with the mainstream. Except for the few that need 24 and 32 cores, two years is a wait. Then again, that only changes it by two months, so eh. But I really want that 7nm.

So says my morning ramblings before I have my coffee (take served with salt)....

 

In the interview with Jim Anderson @ AMD he mentioned that the sales of the TR1 were predominantly 16 core.

AMD offering only a new 32 core TR2, while letting TR1 fill the 16 core role, and then AMD will sell out of the TR1 8c / 12c. Maybe there is enough TR1 production done to sell out TR1 until the 7nm product release?

Whether it makes sense for AMD to fund 2 SKU's for TR2 to allow a cheaper buy-in with a 24 core TR2, IDK.

If TR1 customers bought the top TR1 16c SKU overwhelmingly, AMD is probably weighing the benefits of outfitting a whole SKU for 24 core vs putting all their efforts into the more desireable 32 core + waiting for 7nm to refit the whole TR3 line with all new SKU's.

The 7nm Zen 2.0 may be 6 months away, or?

 

Makes sense and I am less out there with my ramblings (mostly through my first cup of coffee).

The 7nm Zen 2.0 Epyc sampling is 6 months away. We are 9-10 months from Ryzen 3000, a year from Epyc 2, and 13-14 months from TR3. Now, for all those that talk **** on AMD missing release windows, ever since Ryzen, they have been hitting releases, with the exceptions of low availability and some skus having no availability on Epyc last year, and for Vega which seemed HBM2 related (don't want to cover it all, but this is far and away a huge turn around). Compare that with Intel's erratic release schedule, constantly changing roadmap, pushing back releases BY YEARS, etc. They are doing well. I do not want to give the perception they are not. But more the tired rantings of someone that has desires. LOL.

REPOSTING THIS ANALYSIS FROM THE AMD THREAD:
"[A] stock TR 1950X with stock mem is between 2900 and 3100, with all core on 3.7GHz with 2133 loose timings. That is 26.18points per thread per ghz. If you take that, then a perfect linear scaling of the 3100 score would give you 6904 for the CB15 score for 32 Cores at 4.12GHz. The 6399 score is 7.3% slower than perfect linearity. At 2900 we get 24.49 points per thread per GHz, which would scale to 6458 points. So ... this [may be] just a very non-tuned rig the reporter examined. That means it is losing 1%-7.7% score due to the extra dies having no IMC and having to always jump die, which is not outside of the realm of possibility. So ... the ram [could be] slow as **** and it isn't tuned, and we are seeing that, whereas a person that can tune it could toss another 1,000 points on the score, potentially (going from people getting in the 3400-3600 range on CB15 scores, and depending on base, with having double the cores, so just a doubling of the spread from 500 to the 1,000 point number)."

 

Why I said, take it with a grain of salt. We do not know what ram was used, the clock of the ram and what board and PSU.

 

This makes a lot of sense. Fortunately the Taichi has 11 phase but the 16 phase sounds like a must have for 2990x.