Weird things happening with RMClock and quad core

I have been playing around with my Q9200 ES cpu in an 8530w for a couple of weeks now.

I have just noticed that looking at the CPU core/throttle graphs in RMClock, that CPU1 and CPU3 run at a slightly lower speed than CPU0 and CPU2.

Also, RMClock never exits cleanly, and so I always have to "end program" on shutdown.

RMClock runs fine with a dual core in other identical laptos I have, so I am saying this has something to do with the quad.

I'd be interested in any other quad runners comments on this weird situation.

 

Not too surprising considering that RMClock has been developmentally dead for a while now.

 

Well I got the core speeds working properly again by wiping out the registry and starting again. Still doesn't exit cleanly, but I found a registry hack for that.

It just goes to show what a great program RMClock was, since it can still kind of work after years of neglect.

I can't even get any of the "alternatives" (NHC and cpu genie) to actually work at all, they say they are changing VID/FID but CPU-Z says otherwise.

Good thing I'm not planning on upgrading to calpella for another 3 years, because that would really be pushing it.

 

I have heard Crystal CPUID is a good alternative to RMClock. How far have you managed to push your Q9200?

 

HP doesn't allow overclocking of extreme CPUs in their laptops, and they have an undocumented and locked PLL, so I'm SOL as far as overclocking goes. I have undervolted it by about 10% though.

 

Sorry to hear about that. I thought for a moment that it was a destop CPU in your laptop. HP really are partypoopers!

I guess you have located the PLL chip and made sure that no PLL in setfsb will work

 

If you can find the PLL on the motherboard then a quick email to abo (creator of setfsb) will give you support for the PLL.

But it is useless if you have the Montevina platform.

 

Yeah it is montevina, so I guess that means the CPU would self lock to 6x multi?
The PLL is a SLG8SP533V, the only thing I could find out is that it is in fact a PLL IC, other than that I've never heard of SLG.

 

What do you mean by "CPU1 and CPU3 run at a slightly lower speed than CPU0 and CPU2."?

Are you sure its not IDA(Intel Dynamic Accleration) applying to the higher speed cores?

By the way, CPU-Z only refreshes once every second or half a second or so. If the CPU is switching faster than that, CPU-Z wouldn't show.

 

SLG is silego.
Silego makes clock generators.
I can't find the datasheet for your PLL.

The CPU will not lock to 6x multi (unless you do a BSEL mod). There is a different problem with setfsb.
Setfsb does support the PLL. Setfsb does not support montevina.

read this post:
http://forum.notebookreview.com/showpost.php?p=5215722&postcount=6

And the rest of that thread:
http://forum.notebookreview.com/showthread.php?t=409732



Or you could try a hardware PLL mod (I can give you more info on this if you want).

 

I just found it...
http://www.datasheetdir.com/SLG8SP533V+Clock-Synthesizers

It doesn't have any published RW SMBus registers to change clockspeed anyway. The only thing left is a PLL IC pin mod, but I'm not keen on them anymore (I have done it before in the distant past) but it is getting harder lately. And in addition to all this, I'm already pushing the thermal limit of the laptop, since it is not the specifically designed quadcore version.

 

As sure as I can be - the faster core of each die (CPU0 and CPU2 I think) were running at 2.4GHz, their rated speed. The other cores were running at 2.13GHz. I'm pretty sure it was a glitch in RMClock, because it is all working fine now that I reset the config. All working except for the lack of a clean exit.

 

I think Calpella should take care of the problems with weird clock speeds, thread bouncing etc as the CPU will take more control away from the rest of the platform(like the OS) and manage itself like its supposed to be.

 

you can see that bit 6 of byte 9 is the TME bit, because it is a read only bit and it is common for bit 6 of byte 9 to be the TME bit. (if the value is 1 then overclocking will not be allowed, if it is 0 then the PLL is unlocked/overclocking possible).
I'm guessing the M/N programming registers are register (byte) 17 and byte 21.

you can still try setfsb, it may overclock 200mhz.


About the hardware PLL mod:
can you look at pin 5 and see if there is a track comming from it leading to a resistor?

If so then it would be very simple to overclock it.

 

Maybe, there is a resistor or cap coming off pin5, on its way to somewhere else (goes under a big diode)

But I would need to put 0.7V to 1.5V on it, otherwise The PLL would go into "test" mode if any higher.

 

Ok I have tried SetFSB now, and that bit is indeed set to 1, so it is locked.

 

well then your only option is a PLL mod.
too bad


If you do decide to do the PLL mod, take your time and be carefull.
I have modified my PLL as you can see in my sig (the thread about setfsb and clockgen).

Also I killed one of my notebooks trying a simmilar mod.

 

Yeah, me too, that's why I'm not so keen on PLL mods. Having said that, I do have a few spare pre-production versions of 8530p/w mobos that I could play with and not care if I kill. Maybe I will try it one day, you know, when a quad at 2.4GHz just isn't enough anymore.