The waiting is always the worst part![]()
-
Meaker@Sager Company Representative
-
Meaker@Sager Company Representative
sicily428 likes this. -
joluke likes this.
-
Meaker@Sager Company Representative
I've got some engine parts on the way to get my engine rebuilt and it's the same feeling.
jc_denton likes this. -
win32asmguy Moderator Moderator
alaskajoel and jc_denton like this. -
-
Meaker@Sager Company Representative
I don't have download access to them, but they don't tend to be publicly released (officially) since they are copyrighted documents.
-
-
Spartan@HIDevolution likes this.
-
The NVMe drive looks to be running at 2x speeds, which I can only assume is done to allow the SATA drive to connect to the CPU instead of the chipset? I don't imagine there is an option to disable the SATA port in favor of 4x M.2 lanes? Or perhaps the lanes are split equally between the two M.2 slots instead of connecting one via the chipset?
Are all the USB ports connected via the chipset as well?
I'm really looking forward to hearing more of your impressions!
Edit: Nevermind, it looks like one of the PCIe ports is running in gen 2.0 and the other is running in gen 3.0. This makes way more sense! Still curious if the USB 3.1 ports are via chipset or CPU.Last edited: Apr 26, 2020 -
Meaker@Sager Company Representative
If you are confused you can always look up chipset diagrams for the platform. Typically the CPU just has PCI-E lanes coming from it.
-
Assuming this is bog standard B450, there are 16x GPU lanes and 4x lanes split in one of a few configurations. Seeing a 970 EVO benchmark from one of the few reviews published clearly showed it was being limited to ~2GB/s. This can either be because:
- The 4x Gen3 CPU lanes are split in half between the two M.2 slots
- The 4x Gen3 CPU lanes are split between 2x NVME + up to 2x 6Gbps SATA
- The 4x Gen3 CPU lanes go directly to one M.2 slot and SATA + 4x Gen2 NVMe comes from the chipset. This is what I assume is happening on this board now, but don't know for certain.
- The 4x Gen3 CPU lanes are split in half between the two M.2 slots
-
win32asmguy Moderator Moderator
Last edited: Apr 26, 2020Papusan and alaskajoel like this. -
Meaker@Sager Company Representative
Exactly, the chipset handles all the I/O other than the 20 other lanes from the CPU.
The CPU lanes are limited to PCI-E Gen 3 for routing and power reasons. -
-
win32asmguy Moderator Moderator
alaskajoel and Papusan like this. -
Have to wonder if AMD will ever get a Radeon or Radeon Pro mobile chip together that will work with their mobile CPUs?
Why rely on Nvidia? -
There is also some Asus TUF with AMD card and an Acer Nitro with the 560X.
I know this thanks to my database. -
Meaker@Sager Company Representative
USB-C ports can have multiple inputs to them depending on their feature set, nothing stops the USB part being from a chipset and the displayport injected from the GPU for example.Guntraitor Sagara and joluke like this. -
Last edited: Apr 29, 2020
-
Spartan@HIDevolution likes this.
-
Meaker@Sager Company Representative
Yes, in terms of performance per watt, support and drivers there really is not much competition at the moment.
I'd actually say the drivers are the biggest issue. -
Meaker@Sager Company Representative
According to them, the Type-C is from the CPU, rest is chipset. -
Schenker announces XMG Ultra 17 notebook with Core i9-10900K and RTX 2080 SUPER
https://videocardz.com/newz/schenke...tebook-with-core-i9-10900k-and-rtx-2080-super
Spartan@HIDevolution, lestat2k7, Eclipse251 and 5 others like this. -
Notebookbackbreaker Notebook Consultant
-
Spartan@HIDevolution likes this.
-
Notebookbackbreaker Notebook Consultant
. Wonder if the 330W PSU with me can keep up.
jc_denton likes this. -
Spartan@HIDevolution, Papusan, joluke and 1 other person like this.
-
Falkentyne Notebook Prophet
https://cdrdv2.intel.com/v1/dl/getContent/615211
There's something very wrong with the 8 and 6 core Loadline and Amps ratings. This is Skylake cores, not Pluto Lake...and I'm not going to go into my wall of text anymore.
I'll just say--reduce cores, you increase loadline and reduce ICCMAX. That's how it was on CFL. -
Meaker@Sager Company Representative
I assume they know what they are doing with this.
Papusan likes this. -
Falkentyne Notebook Prophet
Want to take me up on it?
As @Papusan said, it's science.
If you have 10 cores, max 24 amps per core, you don't make 8 cores with max 30.5 amps per core, then 6 cores with max 24 amps per core again. Otherwise 9900k could have had 245A also, but at the 1.6 mOhm loadline, that would be:
1520mv - (1.6 * 245) =1.128v at 245 amps with 30 amps per core. No, you are not cooling 245 amps on ANY sort of cooling except sub-ambient.
Every previous generation of chips REDUCED the ICCMAX with each core reduction amount.
Go look at 9th gen yourself if you don't believe me. Do any of the 8th, 9th or even 7th gen KBL chips have 30 amps per core?
https://www.intel.com/content/www/u...core/8th-gen-core-family-datasheet-vol-1.html
Remember this is the company that said up to 4.8 ghz cock speed, before the graphic was pulled ...alaskajoel, Papusan, joluke and 1 other person like this. -
But, yeah 245A is a ton of current. Perhaps Intel will send out a Hailea HC-1000B with the 10900K press kits, lol.Spartan@HIDevolution and joluke like this. -
Falkentyne Notebook Prophet
The 8 core part should be 192 and the 6 core part should be 140. Notice 140 is right next to 138 of the 9600K and 8700K/8086K 6 core parts. And the 6 core loadline is also incorrect electrically. Unless these are not 14nm+++++++ skylake cores...
So why would 8 core be 245 amps?
Not only that, the loadline didn't change either. The loadline must change because these are guidelines for Intel's absolute maximum ratings.
Just do the math. The math is easy.
10900k:
(please ignore "offset capability" for SVID--that's for sub-zero users--note that Gigabyte disabled offset capability by default while I believe Asus enables it by default):
1520mv - (245 * 1.1) = 1.250v @ 245 amps)
10700k:
1520mv - (245 * 1.1) = 1.250v @ 245 amps. BUT THERE ARE TWO FEWER CORES! Current can NOT be the same.
So if we adjust for intel's mistake and lower ICCMAX ourselves:
1520mv - (193 * 1.1) =1.307v @ 193 amps. But this can't be right either, because 9900k was:
1520mv - (193 * 1.6)= 1.212v @ 193 amps. So you need to raise loadline when you lower ICCMAX.
to keep the same values as the 10 core: you get:
1520mv - (193 * 1.4)=1.249v (instead of 1.1 loadline I used 1.4 mOhm loadline).
Maths.Last edited: May 4, 2020alaskajoel, Papusan and jc_denton like this. -
alaskajoel, Spartan@HIDevolution, Falkentyne and 2 others like this.
-
Meaker@Sager Company Representative
Falkentyne likes this. -
Is the embargo for 10th gen May 13th?
-
Meaker@Sager Company Representative
Soon (tm)
-
joluke likes this.
-
Meaker@Sager Company Representative
-
Papusan likes this.
-
Taken from 51M R2 thread found by Falkentyne, some 3DMark physics numbers with the 10gen chips.
Papusan likes this. -
Meaker@Sager Company Representative
-
-
Meaker@Sager Company Representative
-
-
Meaker@Sager Company Representative
-
electrosoft Perpetualist Matrixist
Limited run and still the best you can get without slogging through a bunch of 9900k/kf binning. -
electrosoft likes this.
-
Meaker@Sager Company Representative
Yeah I think it will trend down a little but not much. Not enough to tempt me from my 8086k.
-
Clevo 2020
Discussion in 'Sager and Clevo' started by Dakka3, Aug 28, 2019.